HSC-ADC-FIFO5-INTZ Analog Devices Inc, HSC-ADC-FIFO5-INTZ Datasheet - Page 26

• Manufacturer Part Number: HSC-ADC-FIFO5-INTZ
• Description: Interposer Quad/octal ADCs
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-FIFO5-INTZ

• Accessory Type: ADC Interface Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: AD6640
• Lead Free Status / Rohs Status: Supplier Unconfirmed

HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
JUMPERS
Use the legends below to configure the jumpers. On the FIFO evaluation board, Channel 1 is associated with the bottom IDT FIFO chip,
and Channel 2 is associated with the top IDT FIFO chip (closest to the Analog Devices logo).
Table 2. Jumper Legend
Position
In
Out
Position 1 or Position 3
Table 3 Solder Bridge Legend
Position
In
Out
DEFAULT SETTINGS
Table 4 lists the default settings for each model of the FIFO Evaluation Kit. The single channel (SC) model is configured to work with a
single channel ADC using the bottom FIFO, U201. The dual channel (DC) model is configured to work with demultiplexed ADCs (such
as the AD9430). Dual channel ADC settings are shown in a separate column, as are settings for the opposite (top) FIFO, U101 for a single
channel ADC. To align the timing properly, some evaluation boards may require modifications to these settings. Refer to the Clocking
Description section in the Theory of Operation section for more information.
Another useful way to configure the jumper settings easily for various configurations is to consult ADC Analyzer under the Help > About
HSC_ADC_EVALA, and click Setup Default Jumper Wizard. Then click the configuration setting that applies to the application of
interest. A picture of the FIFO board is displayed for that application with a visual of the correct jumper settings already in place.
Table 4. Jumper Configurations
Jumper
No.
J101
J102
J103
J105
J106
J107
J201
J202
J203
J205
J206
J207
J303
J304
J305
J306
J307
J310-13
J314
J315
J401
Single
Channel
Settings,
Default
(Bottom)
Out
Out
In
In
Out
Out
Out
Out
In
In
Out
Out
In
Position 3
Position 3
Out
Out
In
Position 3
Position 1
Position 1
Demultiplexed
Settings
In
In
In
Position 1
Out
Out
In
In
Out
Out
Out
Out
Out
Out
Out
Position 3
Position 3
Out
Out
Position 3
Position 1
Description
Jumper in place (2-pin header)
Jumper removed (2-pin header)
Denotes the position of a 3-pin header. Position 1 is marked on the board.
Description
Solder pads should be connected
Solder pads should not be connected
Dual
Channel
Settings
Out
Out
In
In
Out
Out
Out
Out
In
In
Out
Out
Out
Position 3
Position 3
Out
Out
In
Position 3
Position 1
Position 1
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Single
Channel
Settings
(Top)
Out
Out
In
In
Out
Out
Out
Out
In
In
Out
Out
In
Position 3
Position 3
Out
Out
In
Position 3
Position 1
Position 1
1
Description
Not Used
Not Used
Ground Unused Pins from Input Header
Ground Unused Pins from Input Header
Not Used
Not Used
Not Used
Not Used
Takes the FF Signal on FIFO1 out of the Circuit
Takes the EF Signal on FIFO1 out of the Circuit
Not Used
Not Used
OUT for Interleave and Dual/Ties Write Clocks Together
POS3: Invert Clock out of DS90
POS3: Invert Clock out of DS90
NO Invert from XOR (U302)
NO Invert from XOR (U302)
All Solder Jumpers are Shorted
No Timing Delay
No Timing Delay
WEN Select