HSC-ADC-FIFO5-INTZ Analog Devices Inc, HSC-ADC-FIFO5-INTZ Datasheet - Page 12

• Manufacturer Part Number: HSC-ADC-FIFO5-INTZ
• Description: Interposer Quad/octal ADCs
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-FIFO5-INTZ

• Accessory Type: ADC Interface Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: AD6640
• Lead Free Status / Rohs Status: Supplier Unconfirmed

HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
board. Channel B corresponds to Channel 2 on the FIFO
schematics and the top FIFO on the evaluation board (closest to
the Analog Devices logo). See the Jumpers section for more
information.
Configuring FFT— Defining Available Options
Samples: Choose the number of samples taken to calculate an
FFT. The default is 16 kB samples. Users can choose more or
fewer samples, depending on the application. The maximum
number of samples that can be selected in the software is 64 kB.
However, the FIFO evaluation boards are configured with 32 kB
FIFOs. For single ADCs evaluated with the HSC-ADC-EVALA-
SC model, the maximum number of samples selected should
match the FIFO memory on the evaluation board. For dual
ADCs evaluated with the HSC-ADC-EVALA-DC model, the
maximum number of samples should match the FIFO memory
of each channel (a different number of samples can be selected
for each channel). ADCs with demultiplexed outputs (such as
the AD9430) can be used with a sample value of twice the FIFO
memory. See the Upgrading FIFO Memory section.
Averages: Specify the number of averages taken for the average
FFT functions. See the ADC Analyzer Functions section for
more information.
Encode Frequency (MHz): Enter the speed of the sampling
clock to the ADC. If evaluating a dual ADC, two different clock
rates can be entered. Note: If the value is wrong, the analog
fundamental frequency displayed will be wrong.
FullScale Input Power (dBm): This feature lets the user enter
the amount of power (in dBm) needed on the input to
determine the output fullscale. It applies only in noise figure
and IIP2/IIP3 calculations.
Enable Fundamental Override: ADC Analyzer automatically
defaults the highest spur as the fundamental frequency of
interest. However, in some applications, the user may have a
very small analog input signal that could be equal to or below
another spurious harmonic. This option lets the user specify the
small analog input signal needed for evaluation. If Enable
Fundamental Override is checked, the Fundamental
Frequency (MHz) box is enabled for the user to specify.
Fundamental Leakage: The number of bins that are neglected
on either side of the fundamental signal when calculating the
SNR and SINAD results. For example, if an encode rate is
defined at 80 MSPS with 16384 samples, then
80M/21/(16384/21) = 4883 Hz/Bin is specified. The type of
windowing selected determines the default value of the
fundamental leakage. See the Windowing section for more
information. The default values are 25, 10, and 1 for Hanning,
Blackman Harris, and no windowing, respectively.
Harmonic Leakage: The number of bins that are neglected on
either side of each harmonic of the fundamental signal defined
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in the Max # of Harmonics’ box. Typically, this can be left at the
default value of 3.
DC Leakage: The number of bins (at dc) that are not used in
calculating SNR and SINAD. Typically, this can be left at the
default value of 6.
Maximum Number of Harmonics: The number of harmonics
displayed by ADC Analyzer. The default value is 6 and the
maximum number of harmonics that can be displayed is 12.
Twos Complement: Check this box if the data from the ADC
evaluation board is in twos complement format. Refer to the
ADC data sheet to determine if the ADC outputs are configured
for twos complement or offset binary. If the Twos Complement
option is not checked, ADC Analyzer will expect the data
outputs from the ADC to be in offset binary format.
User Defined SNR Left (MHz): This is the amount of
frequency specified to the left of the fundamental by the user to
analyze SNR. The resulting value is called UDSNR and will
show up after an FFT plot is captured.
User Defined SNR Right (MHz): This is the amount of
frequency specified to the right of the fundamental by the user
to analyze SNR. The resulting value is called UDSNR and will
show up after an FFT plot is captured.
After configuring the options for the Fast Fourier Transform
plot in this window, click OK.
3.
Step 3
Click OK, and the Buffer Configuration window opens. ADC
Analyzer automatically seeks a USB connection. If a USB
connection is not found, it will assume that you want to use an
older version FIFO board which has a parallel connection. If so,
choose the appropriate parallel connection made to the
computer and click OK.
Choose Config > Buffer. HSC-ADC-EVAL(A), opening the
Buffer Memory screen.