EVAL-AD1937AZ Analog Devices Inc, EVAL-AD1937AZ Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD1937AZ
• Description: EB Single Chip Codec 4 ADCs W/Diff Outp
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1937AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1937
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 112dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), I2C, and SPI Interface, Popguard® Technology
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Evaluation Board User Guide
For the full flexibility of the AD1937/AD1939, the part can be
put in SPI/I
Automated Register Window Builder application (see Figure 4
and Figure 5 for the appropriate jumper settings). Changing the
registers and setting the DIP switches allow many possible
configurations. In the various master and slave modes, the
AD1937/AD1939 take MCLK from a selected source and can be
set to generate or receive either BCLK or LRCLK to or from
either the ADC or the DAC port, depending on the settings and
requirements.
As an example, to set the ADC port as master, switch the ADC
Control 2 register bits for BCLK and LRCLK to master, and
change SW2, Position 2 and Position 5, to on. In this mode, the
board is configured so that the ADC BCLK and LRCLK pins are
the clock source for both the ADC destination and the DAC
data source. For the DAC port to be the master, the DAC
Control 1 register bits for BCLK and LRCLK must be changed
to master, and SW2, Position 2 and Position 3, and SW2, Position 5
and Position 6, must all be on. On this evaluation board, these
settings allow the master port on the AD1937/AD1939 to drive
both the S/PDIF and the HDR connections. Many combinations
of master and slave are possible (see Figure 17 and Figure 18 for
the correct settings).
S/PDIF Audio
The settings in Figure 17 and Figure 18 show the details of clock
routing and control for both the ADC and DAC ports. The
board is shipped with the S/PDIF port selected as the default;
the hex switches are set to 0, and all DIP switches are set to off.
The AD1937/AD1939 are shipped in standalone slave mode
(see Figure 2); the BCLK and LRCLK signals run from the S/PDIF
receiver to both ADC and DAC ports of the AD1937/AD1939.
2
C control mode and programmed with the
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In this default configuration, the DAC audio path routes the
S/PDIF audio signal to all four stereo AD1937/AD1939 DSDATA
inputs simultaneously. The rotary switch, S4, allows the user to
select individual stereo pairs for transmission of the analog
signal. Position 0 is the default; Position 1 to Position 4 allow the
S/PDIF input signal to be assigned to Pair 1 to Pair 4, respectively.
Also in this default configuration, IN1 analog is routed through
the AD1937/AD1939 ADC ASDATA1 path to the S/PDIF
output. IN2 is selected by changing the S3 DIP switch, Position 8,
from 0 to 1.
HDR Connectors—Serial Audio
Routing of serial audio to and from the HDR1 connector is con-
trolled by DIP SW3, Position 6 and Position 7, and Rotary S4.
For the DAC audio signal path, S4, Position 8, assigns the data
signal coming into HDR1 DSDATA1 to all four DSDATA ports
on the AD1937/AD1939. S4, Position 9, assigns the HDR1
labeled ports to the associated port on the AD1937/AD1939.
Other Options
It is possible to mute all data going to the DSDATA ports of the
AD1937/AD1939 by selecting S4, Position 7. This shows the
SNR of the DACs.
To use other f
AD1937/AD1939 registers must be programmed accordingly.
For example, adjusting the f
and DAC Control 0 registers have sample rates set to 96 kHz
(see Figure 17 and Figure 18 for the complete list of options).
The CPLD code is presented in the CPLD Code section and is
included with the evaluation board; alterations and additions to
the functionality of the CPLD are possible by altering the code
and reprogramming the CPLD.
S
rates, the USBi must be connected and the
S
rate to 96 kHz requires that the ADC
UG-040