EVAL-AD1937AZ Analog Devices Inc, EVAL-AD1937AZ Datasheet
EVAL-AD1937AZ
Specifications of EVAL-AD1937AZ
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EVAL-AD1937AZ Summary of contents
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FEATURES PLL-generated clock or direct master clock Low EMI design 112 dB DAC/107 dB ADC dynamic range and SNR −96 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24-bits and 8 kHz to ...
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AD1937 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Test Conditions ............................................................................. 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 5 Digital ...
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SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Table 1. Parameter Supply Voltages (AVDD, DVDD) Temperature Master Clock Input Sample Rate Measurement Bandwidth Word Width Load Capacitance (Digital ...
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AD1937 Parameter Total Harmonic Distortion + Noise Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal ...
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Parameter Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode ...
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AD1937 DIGITAL SPECIFICATIONS −40°C < T < +125°C, DVDD = 3.3 V ± 10%. C Table 5. Parameter INPUT High Level Input Voltage ( Low Level Input Voltage ( Input Leakage Input Capacitance OUTPUT High Level ...
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DIGITAL FILTERS Table 7. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode All modes, typical @ ...
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AD1937 TIMING SPECIFICATIONS −40°C < T < +125°C, DVDD = 3.3 V ± 10%. C Table 8. Parameter INPUT MASTER CLOCK (MCLK) AND RESET MCLK f MCLK t PDR t PDRR PLL Lock Time 256 ...
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TIMING DIAGRAMS t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATAx LEFT-JUSTIFIED MSB MODE t DDH DSDATAx 2 I S-JUSTIFIED MODE DSDATAx RIGHT-JUSTIFIED MODE t ABH ABCLK t ABL t ALS ALRCLK t ABDD ASDATAx LEFT-JUSTIFIED MSB MODE ...
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AD1937 ABSOLUTE MAXIMUM RATINGS Table 9. Parameter Analog (AVDD) Digital (DVDD) VSUPPLY Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND MCLKI/MCLKXI MCLKO/MCLKXO AGND AVDD DAC3LP DAC3LN DAC3RP DAC3RN DAC4LP DAC4LN DAC4RP DAC4RN PD/RST DSDATA4 DGND CONNECT Table 11. Pin Function Descriptions 1 Pin No. Type Mnemonic 1, 4, 44, 46, 48 ...
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AD1937 1 Pin No. Type Mnemonic 23 I VSUPPLY 24 I VSENSE 25 O VDRIVE 26 I/O ASDATA2 27 O ASDATA1 28 I/O ABCLK 29 I/O ALRCLK 30 I ADDR0 31 I/O SDA 34 I SCL 35 I ADDR1 36 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0. FREQUENCY (kHz) Figure 5. ADC Pass-Band Filter Response, 48 kHz 0 –10 –20 –30 –40 –50 –60 –70 –80 ...
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AD1937 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 FREQUENCY (kHz) Figure 11. DAC Pass-Band Filter Response, 192 kHz 32 64 Rev Page –2 –4 –6 –8 –10 ...
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THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCs) There are four ADC channels in the AD1937 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ...
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AD1937 To maintain the highest performance possible, limit the clock jitter of the internal master clock signal to less than a 300 ps rms time interval error (TIE). Even at these levels, extra noise or tones can appear in the ...
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SCK SDA START BY MASTER (S) CHIP ADDRESS BYTE SCK SDA START BY MASTER (S) CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) REPEATED START BY MASTER (S) CHIP ADDRESS BYTE ...
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AD1937 2 Table 13 Abbreviation Table Abbreviation Table 14. Single Word I C Write Chip Address, R Table 15. Burst Mode I C Write Chip Address, R ...
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SERIAL DATA PORTS—DATA FORMAT The eight DAC channels use a common serial bit clock (DBCLK) and a common left-right framing clock (DLRCLK) in the serial data port. The four ADC channels use a common serial bit clock (ABCLK) and left-right ...
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AD1937 TIME-DIVISION MULTIPLEXED (TDM) MODES The serial ports of the AD1937 have several different TDM serial data modes. Single-line TDM mode is the most com- monly used configuration (see Figure 16 and Figure 17). These figures show 8-channel configuration; other ...
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ALRCLK ABCLK UNUSED SLOTS DSDATA1 EMPTY EMPTY EMPTY (TDM DATA IN) 32 BITS MSB DLRCLK (AUX LRCLK IN/OUT) DBCLK (AUX BCLK IN/OUT) ASDATA2 MSB (AUX DAC1 DATA OUT) DSDATA4 MSB (AUX DAC2 DATA OUT) ALRCLK ABCLK DSDATA1 DACL1 DACR1 (TDM ...
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AD1937 ALRCLK ABCLK 4 ON-CHIP ADC CHANNELS ASDATA1 ADCL1 ADCR1 ADCL2 (TDM DATA OUT) MSB DLRCLK (AUX LRCLK IN/OUT) DBCLK (AUX BCLK IN/OUT) DSDATA2 (AUX ADC1 DATA IN) DSDATA3 (AUX ADC2 DATA IN) ALRCLK ABCLK UNUSED SLOTS DSDATA1 EMPTY EMPTY ...
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DAISY-CHAIN MODE The AD1937 also allows a daisy-chain configuration to expand the system to 16 DACs and 8 ADCs (see Figure 22 to Figure 26). In this mode, the DBCLK frequency is 512 × f slots of the TDM DAC ...
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AD1937 DLRCLK DBCLK DSDATA1 DAC1L DSDATA2 DAC3L 32 BITS MSB Figure 24. Dual-Line Daisy-Chain TDM Mode 8-Channel 192 kHz DAC Configuration ALRCLK ABCLK 4 ADC CHANNELS OF SECOND IC IN THE CHAIN ASDATA1 (TDM ADC DATA OUT) ADC1L OF THE ...
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Table 19. Pin Function Changes in TDM and TDM/AUX Modes (Replication of Table 18) Mnemonic Stereo Modes ASDATA1 ADC1 data out ASDATA2 ADC2 data out DSDATA1 DAC1 data in DSDATA2 DAC2 data in DSDATA3 DAC3 data in DSDATA4 DAC4 data ...
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AD1937 ADDITIONAL MODES The AD1937 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 28 and Figure 29 for an example ...
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CONTROL REGISTERS DEFINITIONS The global address for the AD1937 is 0x08 OR’ with ADDR1 and ADDR0 and one R/ W bit; see bits (Bits[18:17]) setting must correspond to the low/high state of Pin 30 and Pin 35. All ...
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AD1937 Table 23. PLL and Clock Control 1 Register (Address 1, 0x01) Bit Value Function 0 0 PLL clock 1 MCLK 1 0 PLL clock 1 MCLK 2 0 Enabled 1 Disabled 3 0 Not locked 1 Locked 7:4 0000 ...
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Table 25. DAC Control 1 Register (Address 3, 0x03) Bit Value Function 0 0 Latch in midcycle (normal) 1 Latch in at end of cycle (pipeline) 2 channels) 01 128 (4 channels) 10 256 (8 channels) 11 ...
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AD1937 Table 28. DACxx Volume Controls Registers (Address 6 to Address 13, 0x06 to 0x0D) Bit Value Function 7 attenuation 1 to 254 −0.375 dB per step 255 Full attenuation ADC CONTROL REGISTERS Table 29. ADC Control 0 ...
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Table 31. ADC Control 2 Register (Address 16, 0x10) Bit Value Function 0 0 50/50 (allows 32, 24, 20 BCLKs per channel) 1 Pulse (32 BCLKs per channel Drive out on falling edge (DEF) 1 Drive ...
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AD1937 APPLICATIONS CIRCUITS Typical application circuits are shown in Figure 31 through Figure 34. Figure 31 shows a typical ADC input filter circuit. Recommended loop filters for LRCLK and MCLK as the PLL reference are shown in Figure 32. Output ...
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... Model 1, 2 Temperature Range AD1937WBSTZ –40°C to +125°C AD1937WBSTZ-RL –40°C to +125°C EVAL-AD1937AZ RoHS Compliant Part Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD1937WBSTZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully ...
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AD1937 NOTES Rev Page ...
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NOTES Rev Page AD1937 ...
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AD1937 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07414-0-6/10(B) Rev ...