EVAL-AD1937AZ Analog Devices Inc, EVAL-AD1937AZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD1937AZ
• Description: EB Single Chip Codec 4 ADCs W/Diff Outp
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1937AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1937
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 112dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), I2C, and SPI Interface, Popguard® Technology
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Evaluation Board User Guide
The MCLK configurations shown in Figure 12 and Figure 13
use the
possibly, the HDRs. The passive crystal runs the AD1937/AD1939
at 12.288 MHz. Figure 13 shows the MCLKI shut off; this is the
case when the PLL is set to lock to LRCLK instead of to MCLK.
OSC DISABLE
OSC DISABLE
C158
C158
Figure 10. External Clock In as Master; the AD1939 and CPLD as Slaves
L7
L7
Figure 11. Active On-Board Oscillator as Master; the AD1939 and
AD1937/AD1939
1938_MCLKI
1938_MCLKI
EXT
EXT
R160
R160
U21
U21
CPLD
HDR2
HDR1
HDR2
HDR1
CPLD
HDR2
HDR1
HDR2
HDR1
JP18
JP19
JP18
JP19
JP23
JP25
JP27
JP28
JP29
JP30
JP31
JP23
JP25
JP27
JP28
JP29
JP30
JP31
JP22
8416
JP22
8416
CLK
CLK
193X_MCLKI
193X_MCLKI
DISABLE
DISABLE
CPLD as Slaves
MCLKO port to drive the CPLD and,
R174
R174
JP20
JP20
C168
C168
Y1
Y1
R167
R169
R172
R167
R169
R172
U22
U22
MCLKO
XTAL
MCLKO
XTAL
C170
C170
C147
U18
C147
U18
R175
R175
193X_MCLKO
193X_MCLKO
EXT CLK IN
EXT CLK IN
J22
J23
J22
J23
Rev. 0 | Page 5 of 32
CONFIGURING THE PLL FILTER
The PLL for the AD1937/AD1939 can run from either MCLK
or LRCLK, according to its setting in the PLL and Clock Control 0
register, Bits[6:5]. The matching RC loop filter must be con-
nected to LF (Pin 61) using JP15. See Figure 14 and Figure 15
for the jumper positions.
OSC DISABLE
Figure 12. Passive Crystal; the AD1939 Is Master and the CPLD Is Slave from
OSC DISABLE
Figure 13. LRCLK Is the Master Clock Using the PLL; MCLKI Is Disabled, and
C158
C158
L7
L7
1938_MCLKI
1938_MCLKI
EXT
EXT
R160
R160
U21
U21
CPLD
HDR2
HDR1
HDR2
HDR1
CPLD
HDR2
HDR1
HDR2
HDR1
JP18
JP19
JP23
JP25
JP27
JP28
JP29
JP30
JP31
JP18
JP19
JP23
JP25
JP27
JP28
JP29
JP30
JP31
8416
8416
JP22
JP22
CLK
CLK
193X_MCLKI
193X_MCLKI
CPLD Is Slave to the MCLKO Port
DISABLE
DISABLE
the MCLKO Port
R174
R174
JP20
JP20
C168
C168
Y1
Y1
R167
R169
R172
R167
R169
R172
U22
U22
MCLKO
XTAL
MCLKO
XTAL
C170
C170
C147
U18
C147
U18
R175
R175
193X_MCLKO
193X_MCLKO
EXT CLK IN
EXT CLK IN
UG-040
J22
J23
J22
J23