EPM1270GT144I5N Altera, EPM1270GT144I5N Datasheet - Page 54

• Manufacturer Part Number: EPM1270GT144I5N
• Description: MAX II
• Manufacturer: Altera

Specifications of EPM1270GT144I5N

• Family Name: MAX II
• Memory Type: Flash
• # Macrocells: 980
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 127
• # I/os (max): 116
• Operating Supply Voltage (typ): 1.8V
• In System Programmable: Yes
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Compliant

4–4
Figure 4–2. Transistor-Level Diagram of MAX II Device I/O Buffers
Figure 4–3. ESD Protection During Positive Voltage Zap
MAX II Device Handbook
n+
The CMOS output drivers in the I/O pins intrinsically provide electrostatic discharge
(ESD) protection. There are two cases to consider for ESD voltage strikes: positive
voltage zap and negative voltage zap.
A positive ESD voltage zap occurs when a positive voltage is present on an I/O pin
due to an ESD charge event. This can cause the N+ (Drain)/ P-Substrate junction of
the N-channel drain to break down and the N+ (Drain)/P-Substrate/N+ (Source)
intrinsic bipolar transistor turn on to discharge ESD current from I/O pin to GND.
The dashed line (see
positive ESD zap.
IOE Signal
p - well
I/O
n+
GND
VPAD
Figure
Source
Drain
Drain
Source
PMOS
NMOS
4–3) shows the ESD current discharge path during a
Larger of VCCIO or VPAD
p+
IOE Signal or the
Gate
Gate
Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
n - well
Hot Socketing Feature Implementation in MAX II Devices
P-Substrate
VCCIO
p+
p - substrate
N+
N+
VCCIO or VPAD
The Larger of
D
S
n+
GND
I/O
G
© October 2008 Altera Corporation
Ensures 3.3-V
Tolerance and
Hot-Socket
Protection