EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 796

IC Universal Platform ARM9 SOC Prcessor

EP9307-CRZR

Manufacturer Part Number
EP9307-CRZR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9307-CRZR

Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-LFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
Q5809834A

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
28
28-6
GPIO Interface
EP93xx User’s Guide
28.1.4 GPIO Pin Map
All GPIO signals are mapped to device pins. The Syscon DeviceCfg register contains four
bits that control mapping of the GPIO Ports to device pins: GonK, EonIDE, GonIDE, and
HonIDE.
to EP93xx pins depending on these control signals.
1. GRLED is the Green LED pin.
2. RDLED is the Red LED pin.
3. EECLK is the EEPROM clock pin.
Table
1. GRLED is the Green LED pin.
2. RDLED is the Red LED pin.
3. EECLK is the EEPROM clock pin.
4. EEDAT is the EEPROM data pin.
EGPIO[13:8]
EGPIO[7:0]
EGPIO[15]
ROW[7:0]
COL[7:0]6
GRLED
RDLED
EECLK
EEDAT
Name
28-1,
Pin
Table 28-1. EP9301 and EP9302 GPIO Port to Pin Map
3
4
1
2
5
Table
EGPIO[15:8]
Pin Name
EGPIO[7:0]
Table 28-2. EP9307 GPIO Port to Pin Map
GRLED
RDLED
EECLK
EEDAT
28-2,
Copyright 2007 Cirrus Logic
2
3
4
1
Table
Function
ROW[7:0]
28-3, and
COL[7:0]
Default
Port E0
Port E1
Port G0
Port G1
Port A
Port B
Port B
Table 28-4
Default Function
Port G0
Port G1
Port E0
Port E1
Port A
Port B
show how the GPIO ports map
Function in
Port G0
Port G1
Port E0
Port E1
GonK
Mode
Port A
Port B
Port B
Port C
Port D
DS785UM1

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