EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 226

• Manufacturer Part Number: EP9307-CRZR
• Description: IC Universal Platform ARM9 SOC Prcessor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZR

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-LFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5809834A

7
HBlankStrtStop
7-44
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Address: 0x8003_022C
Default: 0x0000_0000
Definition: Horizontal Blank signal Start/Stop register
Bit Descriptions:
30
14
RSVD
RSVD
29
13
28
12
STRT:
RSVD:
STOP:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Start - Read/Write
The STRT value is the value of the Horizontal down
counter at which the HACTIVE signal becomes active
(starts). This indicates the start of the active video portion
for the Horizontal line. Please refer to video signalling
timing diagrams in
is an internal block signal. The active video interval is
controlled by the logical OR of VACTIVE and HACTIVE.
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HBLANK signal becomes inactive
(stops). This is used to generate the BLANKn signal that is
used by external devices to indicate the end of the active
video portion for the Horizontal line. Please refer to video
signalling timing diagrams in
HBLANK is an internal clock signal. The BLANKn output is
a logical AND of VBLANK and HBLANK.
STRT:Start - Read/Write
The STRT value is the value of the Horizontal down
counter at which the HBLANK signal becomes active
(starts). This is used to generate the BLANKn signal that is
used by external devices to indicate the start of the active
video portion for the Horizontal line. Please refer to video
signalling timing diagrams in
HBLANK is an internal clock signal. The BLANK output is
a logical AND of VBLANK and HBLANK
24
8
23
7
22
6
Figure 7-9
STOP
STRT
21
5
Figure 7-9
Figure 7-9
and
20
4
Figure
19
3
and
and
7-10. HACTIVE
18
2
Figure
Figure
17
1
DS785UM1
7-10.
7-10.
16
0