EP3C16F484I7N Altera, EP3C16F484I7N Datasheet - Page 262

• Manufacturer Part Number: EP3C16F484I7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484I7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

11–8
Cyclone III Device Handbook, Volume 1
1
Figure 11–3
interface that the WYSIWYG atom enables in your design.
Figure 11–3. Error Detection Block Diagram
The user logic is affected by the soft error failure, thus reading out the 32-bit CRC
signature through the regout should not be relied upon to detect a soft error. You
should rely on the CRC_ERROR output signal itself, because this CRC_ERROR output
signal cannot be affected by a soft error.
To enable the <device>_crcblock WYSIWYG atom, you must name the atom for
each Cyclone III device family accordingly.
80MHz Internal Chip Oscillator
(Saved in the Option Register)
SRAM
shows the error detection block diagram in FPGA devices and shows the
Bits
Pre-Computed CRC
Computation
(1 to 256 Factor)
CRC
Clock Divider
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Error Detection
Logic
Logic Array
© December 2009 Altera Corporation
VCC
cyclecomplete
(Shown in BIDIR Mode)
CRC_ERROR
Software Support