EP3C16F484I7N Altera, EP3C16F484I7N Datasheet - Page 178

• Manufacturer Part Number: EP3C16F484I7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C16F484I7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / Rohs Status: Compliant

9–18
Figure 9–5. Multi-Device AS Configuration where the Devices Receive the Same Data with Multiple SRAM Object Files
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AS mode and the slave
(5) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin functions as the DATA[1] pin in
(6) Connect the series resistor at the near end of the serial configuration device.
(7) Connect the repeater buffers between the master and slave devices for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage
(8) The 50-Ω series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50-Ω series
Cyclone III Device Handbook, Volume 1
devices in PS mode. To connect MSEL[3..0] for the master device in AS mode and the slave devices in PS mode, refer to
page
other AP and FPP modes.
of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
Requirements” on page
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
Figure
9–11. Connect the MSEL pins directly to V
Serial Configuration
9–5:
Device
DCLK
DATA
ASDI
nCS
9–7.
50
25
Ω
10
(6),
Ω
V CCIO (1)
kΩ
(6)
(8)
GND
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
CCIO
CCIO
DATA[0]
nSTATUS
CONF_DONE
nCONFIG
nCE
DCLK
nCSO (5)
ASDO (5)
10
supply voltage of the I/O bank in which the nCE pin resides.
supply of the bank in which the pin resides.
V CCIO (1)
kΩ
Master Device of the
Cyclone III Device
50
Ω
Family
Buffers (7)
CCA
(8)
10
or GND.
MSEL[3..0]
V CCIO (1)
kΩ
nCEO
10
V CCIO (2)
kΩ
(4)
Slave Device of the Cyclone III Device Family
Slave Device of the Cyclone III Device Family
Slave Device of the Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
© December 2009 Altera Corporation
MSEL[3..0]
MSEL[3..0]
MSEL[3..0]
“Configuration and JTAG Pin I/O
nCEO
nCEO
nCEO
Configuration Features
Table 9–7 on
N.C. (3)
(4)
N.C. (3)
(4)
N.C. (3)
(4)