CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 43

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CS4202-JQZR

Manufacturer Part Number
CS4202-JQZR
Description
IC AC97 W/Headphone Amplifier
Manufacturer
Cirrus Logic Inc
Type
Audio Codec '97r
Datasheet

Specifications of CS4202-JQZR

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
90 / 90
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TQFP, 48-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4202-JQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
5.3
In order to support a wide variety of serial audio
DACs, the CS4202 can transmit serial data in four
different formats. The desired format is selected
through the SDF[1:0] bits in the Serial Port Control
Register (Index 6Ah). All serial ports use the same
serial data format when enabled. In all cases, LR-
CLK will be synchronous with Fs, and SCLK will
DS549PP2
SDATA
SDATA
SDATA
SDATA
LRCK
LRCK
LRCK
SCLK
LRCK
SCLK
SCLK
SCLK
1 0
Serial Data Formats
SDF[1:0]
0 0
0 1
1 0
1 1
M S B-1 -2 -3 -4 -5
M S B-1 -2 -3 -4 -5
19 18
Polarity
negative
17 16
LRCLK
positive
positive
positive
15 14 13 12 11 10
Table 14. Serial Data Formats and Compatible DACs for the CS4202
15 14 13 12 11 10
Figure 13. Serial Data Format 2 (Right Justified, 20-bit data)
Left Channel
Figure 14. Serial Data Format 3 (Right Justified, 16-bit data)
Left Channel
Justification
right justified
right justified
left justified
left justified
+5 +4
+5 +4
Left Channel
Left Channel
Data
Figure 12. Serial Data Format 1 (Left Justified)
+3 +2 +1 LSB
+3 +2 +1 LSB
9 8 7
9 8 7
Figure 11. Serial Data Format 0 (I
(MSB vs. LRCLK)
6 5 4 3 2 1 0
Data Alignment
1 SCLK delayed
6 5 4 3 2 1 0
not delayed
not delayed
not delayed
be 64 Fs (BIT_CLK/4). Serial data is transitioned by
the CS4202 on the falling edge of SCLK and latched
by the DACs on the next rising edge. Serial data is
shifted out MSB first in all supported formats, but
LRCLK polarity as well as data justification, align-
ment, and resolution vary. Table 14 shows the prin-
cipal characteristics of each serial format.
Resolution
19 18
M SB-1 -2 -3 -4
M S B-1 -2 -3 -4
20-bit
20-bit
20-bit
16-bit
Data
17 16
2
15 14 13 12 11 10
S)
15 14 13 12 11 10
Diagram
Figure 11
Figure 12
Figure 13
Figure 14
Timing
+5 +4
+5 +4
Right Channel
Right Channel
Right Channel
Right Channel
+3 +2 +1 LSB
+3 +2 +1 LSB
9 8 7
Recommended
9 8 7
CS4334
CS4335
CS4337
CS4338
DAC
6 5 4 3 2 1 0
6 5 4 3 2 1 0
CS4202
43

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