CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 30

• Manufacturer Part Number: CS4202-JQZR
• Description: IC AC97 W/Headphone Amplifier
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.12
ID[1:0]
REV[1:0]
AMAP
DSA[1:0]
SPDIF
VRA
Default
30
D15
ID1
Extended Audio ID Register (Index 28h)
D14
ID0
D13
0
CS4202 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4202 is a secondary
audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins
and the current clocking scheme, see Table 18 on page 49.
dec complies with. These bits always return ‘01’, indicating the CS4202 complies with
version 2.2 of the AC ’97 specification.
audio DAC mapping is supported. This bit always returns ‘1’, indicating that audio slot map-
ping is supported. The PCM playback and capture slots are mapped according to Table 8 on
page 30.
block as well as the serial data port. To satisfy AC ‘97 2.2 AMAP requirements, the default for
these bits will depend on the Codec ID as shown in Table 9. See Table 8 for all available Slot
Map settings.
mitter is supported.
ed. This bit always returns ‘1’, indicating that variable rate PCM audio is available.
DSA[1:0] bits which are read/write.
Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the
AC ’97 Revision. The REV[1:0] bits indicate which version of the AC ’97 specification the co-
Audio Slot Mapping. The AMAP bit indicates whether the AC ’97 2.2 compliant AC-link slot to
DAC Slot Assignment. The DSA[1:0] bits control the mapping of output slots to the DAC/SRC
Sony/Philips Digital Interface. The SPDIF bit is ‘set’, indicating that the optional S/PDIF trans-
Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is support-
x605h. The Extended Audio ID Register (Index 28h) is a read-only register, except for the
D12
Slot Assignment
SPSA1
0
DSA1
ASA1
Codec ID
0
0
1
1
REV1 REV0 AMAP
0
1
2
3
D11
SPSA0
DSA0
ASA0
0
1
0
1
D10
Table 9. Slot Assignment Defaults
DSA[1:0]
default
00
01
01
10
D9
10
L
3
7
6
DAC
Table 8. Slot Mapping for the CS4202
D8
11
R
4
8
9
0
SPSA[1:0]
default
10
D7
L
7
6
01
10
10
11
0
SDOUT
-
11
D6
R
8
9
0
-
Slot Mapping
DSA1 DSA0
ASA[1:0]
10
D5
default
L
6
-
-
SDO2
00
00
00
00
D4
11
R
9
-
-
10
D3
L
3
7
6
0
S/PDIF
SPDIF
D2
11
R
4
8
9
CS4202
D1
L
3
7
6
0
-
DS549PP2
ADC
VRA
D0
11
R
4
8
-