CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 15

• Manufacturer Part Number: CS4202-JQZR
• Description: IC AC97 W/Headphone Amplifier
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. AC-LINK FRAME DEFINITION
The AC-link is a bi-directional serial port with data
organized into frames consisting of one 16-bit and
twelve 20-bit time-division multiplexed slots.
Slot 0 is a special reserved time slot containing
16-bits which are used for AC-link protocol infra-
structure. Slots 1 through 12 contain audio or con-
trol/status data. Both the serial data output and
input frames are defined from the controller per-
spective, not from the CS4202 perspective.
The controller synchronizes the beginning of a
frame with the assertion of the SYNC signal.
Figure 9 shows the position of each bit location
DS549PP2
Bit Frame Position:
SDATA_OUT
Bit Frame Position:
SDATA_IN
BIT_CLK
SYNC
F255
F255
GPIO
81.4 ns
INT
0
Frame
Codec
Ready
Valid
F0
F0
12.288 MHz
Slot 1
Slot 1
Valid
Valid
F1
F1
Slot 2
Slot 2
Valid
Valid
F2
F2
Tag Phase
Figure 9. AC-link Input and Output Framing
Slot 0
Slot 12
Slot 12
F12
Valid
F12
Valid
F13
F13
0
0
Codec
F14
F14
ID1
0
Codec
F15
F15
ID0
0
F16
R/W
F16
(48 kHz)
20.8 µ s
0
Slot 1
within the frame. The first bit position in a new se-
rial data frame is F0 and the last bit position in the
serial data frame is F255. When SYNC goes active
(high) and is sampled active by the CS4202 (on the
falling edge of BIT_CLK), both devices are syn-
chronized to a new serial data frame. The data on
the SDATA_OUT pin at this clock edge is the final
bit of the previous frame’s serial data. On the next
rising edge of BIT_CLK, the first bit of Slot 0 is
driven by the controller on the SDATA_OUT pin.
On the next falling edge of BIT_CLK, the CS4202
latches this data in as the first bit of the frame.
F35
F35
0
0
WD15
RD15
F36
F36
Slot 2
Data Phase
D19
D19
F56
F56
Slot 3
F57
D18
D18
F57
D19
D19
F76
F76
Slot 4
D19
D19
F96
F96
CS4202
Slots 5-12
F255
F255
GPIO
INT
0
15