CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 36

• Manufacturer Part Number: CS4202-JQZR
• Description: IC AC97 W/Headphone Amplifier
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.21
GW[4:0]
Default
GPIO bits which have been programmed as inputs, “sticky”, and “wakeup”, upon transition either (high-to-low) or
(low-to-high) depending on pin polarity, will cause an AC-link wakeup if and only if the AC-link was powered down.
Once the controller has re-established communication with the CS4202 following a Warm Reset, it will continue to
signal the wakeup event through the GPIO_INT bit of input Slot 12 until the AC ’97 controller clears the inter-
rupt-causing bit in the GPIO Pin Status Register (Index 54h); or the “wakeup”, config, or “sticky” status of that GPIO
pin changes.
After a Cold Reset or a modem Register Reset (see Extended Modem ID Register (Index 3Ch)) this register defaults
to all 0’s, specifying no wakeup event. The upper 11 bits of this register always return ‘0’.
4.22
GI[4:0]
Default
GPIO pins which have been programmed as inputs and “sticky”, upon transition either (high-to-low) or (low-to-high)
depending on pin polarity, will cause the individual GI bit to be ‘set’, and remain ‘set’ until ‘cleared’. GPIO pins which
have been programmed as outputs are controlled either through output Slot 12 or through this register, depending
on the state of the GPOC bit in the Misc. Crystal Control Register (Index 60h). If the GPOC bit is ‘cleared’, the GI
bits in this register are read-only and reflect the status of the corresponding GPIO output pin ‘set’ through output
slot 12. If the GPOC bit is ‘set’, the GI bits in this register are read/write bits and control the corresponding GPIO
output pins.
The default value is always the state of the GPIO pin. The upper 11 bits of this register should be forced to zero in
this register and input Slot 12.
4.23
ASPM
36
D15
D15
D15
0
0
0
GPIO Pin Wakeup Mask Register (Index 52h)
GPIO Pin Status Register (Index 54h)
AC Mode Control Register (Index 5Eh)
D14
D14
D14
0
0
0
D13
D13
D13
0
0
0
GPIO Pin Status. This register reflects the state of all GPIO pin inputs and outputs. These
values are also reflected in Slot 12 of every SDATA_IN frame. GPIO inputs configured as
“sticky” are ‘cleared’ by writing a ‘0’ to the corresponding bit of this register. The GPIO_INT
bit in input Slot 12 is ‘cleared’ by clearing all interrupt-causing bits in this register.
0000h
When ‘clear’, the S/PDIF transmitter will receive data from the corresponding AC-link output
slots. The actual slots are determined by the state of the SPSA[1:0] bits in the Extended Audio
Status/Control Register (Index 2Ah). If ‘set’, the S/PDIF transmitter block will receive data
GPIO Pin Wakeup. This register provides a mask for determining if an input GPIO change will
generate a wakeup event (0 = no, 1 = yes). When the AC-link is powered up, a wakeup event
will be communicated through the assertion of GPIO_INT = 1 in input Slot 12. When the
AC-link is powered down (Powerdown Control/Status Register (Index 26h) bit PR4 = 1 for pri-
mary codecs), a wakeup event will be communicated through a ‘0’ to ‘1’ transition on
SDATA_IN.
0000h
Analog S/PDIF Mode. The ASPM bit controls the input source to the S/PDIF transmitter block.
D12
D12
D12
0
0
0
ASPM
D11
D11
D11
0
0
D10
D10
D10
0
0
0
TMM
D9
D9
D9
0
0
DDM
D8
D8
D8
0
0
D7
D7
D7
0
0
0
D6
D6
D6
0
0
0
ASA1 ASA0
D5
D5
D5
0
0
GW4
D4
GI4
D4
D4
GW3
D3
GI3
D3
D3
0
GW2
GI2
D2
D2
D2
0
GW1
CS4202
GI1
D1
D1
D1
DS549PP2
0
GW0
GI0
D0
D0
D0
0