CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 40

• Manufacturer Part Number: CS4202-JQZR
• Description: IC AC97 W/Headphone Amplifier
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.26
E[15:0]
Default
The BDI Config Register (Index 70h) enables BIOS-Driver communication for each possible event. If a bit is ‘0’, the
The BDI Wakeup Register (Index 72h) provides a mask for determining if a BDI event will generate a wakeup or
4.27
E[15:0]
Default
The BDI Status Register (Index 7Ah) reflects the state of all possible events. If a bit is ‘0’, the corresponding event
40
corresponding event will not be communicated. If a bit is ‘1’, the corresponding event will be communicated by as-
serting the BDI bit in input slot 12. If an event occurs, the BIOS will ‘set’ the corresponding bit in the BDI Status Reg-
ister (Index 7Ah). This bit remains ‘set’ until it is cleared by the driver, acknowledging the event has been handled.
This behavior is equivalent to “non-sticky” (level sensitive) GPIO input pins.
GPIO_INT. If a bit is ‘0’, the corresponding event will not generate an interrupt. If a bit is ‘1’, the corresponding event
will generate an interrupt. Refer to the GPIO Pin Wakeup Mask Register (Index 52h) for details about wakeup inter-
rupts.
has not occurred or has already been handled by the driver. If a bit is ‘1’, the corresponding event has occurred and
has not been handled by the driver yet. The BDI bit in input slot 12 is a logic OR of all bits in this register ANDed
with their corresponding bit in the BDI Config Register (Index 70h). After handling an event, the driver should clear
it by writing a ‘0’ to the corresponding bit of this register.
D15
E15
D15
E15
BIOS-Driver Interface Control Registers (Index 70h - 72h)
BIOS-Driver Interface Status Register (Index 7Ah)
D14
E14
D14
E14
D13
D13
E13
E13
Event Configuration. The E[15:0] bits control the BIOS-Driver Interface mechanism.
0000h
Event Status. This register, in conjunction with the BIOS-Driver Interface Control Registers
(Index 70h - 72h), controls the BIOS-Driver Interface mechanism.
0000h
D12
E12
D12
E12
D11
E11
D11
E11
D10
E10
D10
E10
D9
D9
E9
E9
D8
E8
D8
E8
D7
D7
E7
E7
D6
E6
D6
E6
D5
D5
E5
E5
D4
D4
E4
E4
D3
E3
D3
E3
D2
D2
E2
E2
CS4202
D1
E1
D1
E1
DS549PP2
D0
D0
E0
E0