CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet
CS4202-JQZ
Specifications of CS4202-JQZ
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CS4202-JQZ Summary of contents
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... Coupling the CS4202 with a PCI audio accelerator or core logic supporting the AC ’97 interface implements a cost effective, superior quality audio solution. The CS4202 surpasses PC 99, PC 2001, and AC ’97 2.2 au- dio quality standards. ORDERING INFO CS4202-JQZ, Lead Free 48-pin TQFP 9x9x1.4 mm REGISTERS PWR TEST MGT PCM_DATA ...
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... DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. 2 ..................................................................................................... 22 CS4202 DS549PP2 ...
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... MHz Crystal Operation ........................................................................................ 49 9.3 Secondary Codec Operation ........................................................................................... 49 10. ANALOG HARDWARE DESCRIPTION ............................................................................... 51 10.1 Analog Inputs ................................................................................................................. 51 10.1.1 Line Inputs ........................................................................................................ 51 10.1.2 CD Input ............................................................................................................ 51 10.1.3 Microphone Inputs ............................................................................................ 51 10.1.4 PC Beep Input ................................................................................................... 52 10.1.5 Phone Input ....................................................................................................... 52 10.2 Analog Outputs .............................................................................................................. 52 10.2.1 Stereo Outputs .................................................................................................. 52 10.2.2 Mono Output ..................................................................................................... 53 10.3 Miscellaneous Analog Signals ....................................................................................... 53 DS549PP2 CS4202 3 ...
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... Figure 22. Modem Connection ...................................................................................................... 52 Figure 23. Line Out and Headphone Out Setup............................................................................ 53 Figure 24. Line Out/Headphone Out Setup................................................................................... 53 Figure 25. +5V Analog Voltage Regulator..................................................................................... 54 Figure 26. Conceptual Layout for the CS4202 when in XTAL or OSC Clocking Modes ............... 55 Figure 27. Pin Locations for the CS4202 ...................................................................................... 56 Figure 28. CS4202 Reference Design .......................................................................................... 64 4 ...
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... Table 11. GPIO Input/Output Configurations.................................................................... 36 Table 12. Serial Data Format Selection............................................................................ 40 Table 13. Device ID with Corresponding Part Number..................................................... 42 Table 14. Serial Data Formats and Compatible DACs for the CS4202 ............................ 44 Table 15. Powerdown PR Bit Functions ........................................................................... 47 Table 16. Powerdown PR Function Matrix for the CS4202 .............................................. 48 Table 17. Power Consumption by Powerdown Mode for the CS4202 ............................. 48 Table 18 ...
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... D-A A-D SNR D-A THD+N A-A A-A D-A (all inputs) A-D (Note 4) (Note 4) (Note 4) refers to the digital output pin loading. DL CS4202 = 25° C, ambient =100 kΩ/ AL CS4202-JQZ Min Typ Max 0.91 1.00 - 0.91 1.00 - 0.283 0.315 - 0.091 0.10 - 0.0283 0.0315 - 0.91 1.0 1 ...
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... AVss2 = DVss1 = DVss2 = 0 V) +3.3 V Digital +5 V Digital Analog (Supplies, Inputs, Outputs) (Except Supply Pins) (Except Supply Pins) (Power Applied) (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Symbol +3.3 V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 CS4202 CS4202-JQZ Min Typ Max 730 - - 0 ...
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... Output Leakage Current (Tri-stated AC-link outputs) Output buffer drive current BIT_CLK, SDATA_IN SPDIF_OUT EAPD/SCLK, GPIO0/LRCLK, GPIO1/SDOUT, GPIO2, GPIO3, GPIO4/SDO2 8 (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Symbol Min 2. 3. -10 - (Note 3. 4. -10 - (Note 4) - CS4202 Typ Max Unit - 0. 3. 0.03 0. µ µ 0. 4. 0.03 0. µA ...
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... T clk_low F sync T sync_period T sync_high T sync_low isetup T ihold T irise T ifall (Note 4) T orise (Note 4) T ofall T s2_pdown T 1.0 sync_pr4 T 162.8 sync2clk setup2rst (Note 4) T off CS4202 = 25° C, ambient Typ Max Unit µ µs - 4.0 - µ µs - 62.5 - µ 12.288 - MHz - 81 750 ...
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... BIT_CLK RESET# Vdd BIT_CLK SYNC CODEC_READY Figure 2. Codec Ready from Start-up or Fault Condition BIT_CLK T orise SYNC T irise 10 T rst_low T vdd2rst# Figure 1. Power Up Timing T sync2crd clk_high clk_low clk_period T ifall T T sync_high sync_low T sync_period Figure 3. Clocks CS4202 T rst2clk T ifall DS549PP2 ...
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... Slot 1 SDATA_OUT Write to 0x20 SDATA_IN SYNC RESET# SDATA_OUT, SYNC SDATA_IN, BIT_CLK DS549PP2 isetup Figure 4. Data Setup and Hold Slot 2 Data PR4 Don't Care T s2_pdown Figure 5. PR4 Powerdown and Warm Reset T setup2rst T off Figure 6. Test Mode T ihold T T sync_pr4 sync2clk Hi-Z CS4202 11 ...
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... During each au- dio frame, data is passed bi-directionally between the CS4202 and the controller. The input frame is driven from the CS4202 on the SDATA_IN line. The output frame is driven from the controller on the SDATA_OUT line ...
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... Sample Rate Converters The sample rate converters (SRC) provide high ac- curacy digital filters supporting sample frequencies other than 48 kHz to be captured from the CS4202 or played from the controller. AC ’97 requires sup- port for two audio rates (44.1 and 48 kHz). In addi- ® ...
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... INPUT MIXER Σ Σ ANALOG STEREO OUTPUT MIXER MONO MIX STEREO TO SELECT MONO MIXER Σ 1/2 Σ STEREO TO MONO MIXER 1/2 Figure 8. CS4202 Mixer Diagram CS4202 MASTER MODE VOLUME OUTPUT MUTE BUFFER HEADPHONE VOLUME HEADPHONE OUT HEADPHONE MUTE AMPLIFIER MONO OUT ...
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... The first bit position in a new se- rial data frame is F0 and the last bit position in the serial data frame is F255. When SYNC goes active (high) and is sampled active by the CS4202 (on the falling edge of BIT_CLK), both devices are syn- chronized to a new serial data frame. The data on the SDATA_OUT pin at this clock edge is the final bit of the previous frame’ ...
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... AC-Link Serial Data Output Frame In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4202 from the AC ’97 controller. Figure 9 illustrates the serial port timing. The PCM playback data being passed to the CS4202 is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’ ...
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... Not Implemented GPIO[4:0] GPIO Pin Control. The GPIO[4:0] bits control the CS4202 GPIO pins configured as outputs. Write accesses using GPIO pin control bits configured as outputs will be reflected on the GPIO pin output on the next AC-link frame. Write accesses using GPIO pin control bits con- figured as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Con- trol Register (Index 60h) is ‘ ...
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... AC-Link Serial Data Input Frame In the serial data input frame, data is passed on the SDATA_IN pin from the CS4202 to the AC ’97 con- troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 15 illus- trates the serial port timing. ...
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... GPIO[4:0] GPIO Pin Status. The GPIO[4:0] bits reflect the status of the CS4202 GPIO pins configured as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the GPIO[4:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the GPIO[4:0] pin control bits in output Slot 12 ...
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... BIT_CLK clock period after the previous SYNC assertion. Upon loss of synchronization with the controller, the CS4202 will ‘clear’ the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the CS4202 will ignore all register reads and writes and will discontinue the transmission of PCM capture data ...
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... E13 E12 E11 E10 E13 E12 E11 E10 E13 E12 E11 E10 Table 1. Register Overview for the CS4202 ID4 MR5 MR4 MR3 MR2 MR1 0 0 MR5 MR4 MR3 MR2 MR1 0 0 MM5 MM4 MM3 MM2 MM1 PV3 PV2 PV1 PV0 0 ...
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... The data in this register is read-only data. Any write to this register causes a Register Reset of the audio control (Index 00h - 3Ah) and Cirrus Logic defined (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4202. 4.2 Analog Mixer Output Volume Registers (Index 02h - 04h) ...
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... See Table 4 on page 25 for further attenuation levels. Default 8008h. This value corresponds attenuation and Mute ‘set’. DS549PP2 D10 D10 D10 CS4202 MM5 MM4 MM3 MM2 MM1 PV3 PV2 PV1 PV0 GN4 GN3 GN2 GN1 D0 MM0 D0 0 ...
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... Table 3. Microphone Input Gain Values CS4202 GN4 GN3 GN2 GN1 10dB = 1, 20dB = 1 +42.0 dB +40.5 dB ... +31.5 dB +30.0 dB +28.5 dB ... -4.5 dB DS549PP2 D0 GN0 ...
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... Table 4. Analog Mixer Input Gain Values Register Index Function 10h Line In Volume 12h CD Volume 14h Video Volume 16h Aux Volume 18h PCM Out Volume Table 5. Analog Mixer Input Gain Register Index GR4 GR3 GR2 CS4202 D1 D0 GR1 GR0 25 ...
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... This value selects the Mic input for both channels. 26 D10 SL2 SL1 SL0 0 0 Sx2 - Sx0 Record Source 000 Mic 001 CD Input 010 Video Input 011 Aux Input 100 Line Input 101 Stereo Mix 110 Mono Mix 111 Phone Input Table 6. Input Mux Selection CS4202 SR2 SR1 DS549PP2 D0 SR0 ...
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... The total range +22.5 dB gain. See Table 7 for further details. Default 8000h. This value corresponds gain and Mute ‘set’. DS549PP2 D10 GL2 GL1 GL0 0 0 Gx3 - Gx0 Gain Level 1111 +22.5 dB … … 0001 +1.5 dB 0000 0 dB Table 7. Record Gain Values CS4202 GR3 GR2 GR1 D0 GR0 27 ...
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... When ‘set’, the MIC2 input is selected. When ‘clear’, the MIC1 input is selected. LPBK Loopback Enable. When ‘set’, the LPBK bit enables the ADC/DAC Loopback Mode. This bit routes the output of the ADCs to the input of the DACs without involving the AC-link. Default 0000h 28 D10 MIX MS LPBK 0 CS4202 DS549PP2 D0 0 ...
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... The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec- tion of the CS4202 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 8, Power Management, for more information on the powerdown functions ...
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... ID[1:0] Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the CS4202 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4202 is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins and the current clocking scheme, see Table 18 on page 49. ...
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... Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at ‘0’. Default 0410h DS549PP2 D10 SPCV CS4202 SPSA1 SPSA0 0 SPDIF 0 D0 VRA 31 ...
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... Variable Rate PCM Audio mode when the VRA bit in the Extended Audio Status/Control Register (Index 2Ah) is ‘set’. If VRA = 0, writes to the register are ignored and the register will always read BB80h. Sample Rate (Hz) 8,000 11,025 16,000 22,050 32,000 44,100 48,000 Table 10. Directly Supported SRC Sample Rates for the CS4202 32 D10 SR9 SR8 SR7 SR6 ...
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... SPSR[1:0] S/PDIF Sample Rate. The SPSR[1:0] bits are mapped to bits 24 and 25 of the channel status block. These bits control the S/PDIF transmitter clock rate. The CS4202 only supports trans- mission at the standard 48 kHz rate, therefore SPSR[1:0] are read-only bits and always return ‘ ...
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... ID[1:0] Codec ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the CS4202 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4202 is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins and the current clocking scheme, see Table 18 on page 49. ...
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... The upper 11 bits of this register always return ‘0’. DS549PP2 D10 GCx GPx Function Configuration 0 0 Output CMOS Drive 0 1 Output Open Drain 1 0 Input Active Low 1 1 Input Active High (default) Table 11. GPIO Input/Output Configurations D10 CS4202 GP4 GP3 GP2 GP1 GS4 GS3 GS2 GS1 D0 GP0 D0 GS0 35 ...
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... AC-link wakeup if and only if the AC-link was powered down. Once the controller has re-established communication with the CS4202 following a Warm Reset, it will continue to signal the wakeup event through the GPIO_INT bit of input Slot 12 until the AC ’97 controller clears the inter- rupt-causing bit in the GPIO Pin Status Register (Index 54h) ...
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... DAC Direct Mode. The DDM bit controls the source of the line and headphone output drivers. When this bit is ‘clear’, the CS4202 stereo output mixer drives the line and headphone out- puts. When this bit is ‘set’, the CS4202 audio DACs (DAC1 and DAC2) directly drive the line and headphone outputs. ...
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... Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit is ‘set’, the CS4202 will mute all analog outputs for the duration of loss of SYNC. If this bit is ‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4202 ex- pects to sample SYNC ‘ ...
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... All ports will use the same format. See Table 12 for available formats. Default 0000h DS549PP2 D10 SDF1 SDF0 Serial Data Format Left Justified 1 0 Right Justified, 20-bit data 1 1 Right Justified, 16-bit data Table 12. Serial Data Format Selection CS4202 SDO2 SDSC SDF1 SDF0 D0 39 ...
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... The BDI bit in input slot logic OR of all bits in this register ANDed with their corresponding bit in the BDI Config Register (Index 70h). After handling an event, the driver should clear it by writing a ‘0’ to the corresponding bit of this register. 40 D10 E10 D10 E10 CS4202 DS549PP2 D0 E0 ...
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... Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII ‘Y’ character. DID[2:0] Device ID. With a value of DID[2:0] = 111, these bits specify the audio codec is a CS4202. REV[2:0] Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is ‘A’. ...
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... Some audio DACs can run in an internal SCLK mode where SCLK is internally derived from MCLK and LRCLK. In this case, SCLK generation in the CS4202 is optional. A feature has been designed into the CS4202 that allows the phase of the internal DACs to be re- versed. This DAC phase reversal is controlled by 35 ...
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... Polarity Justification 0 0 negative left justified 0 1 positive left justified 1 0 positive right justified 1 1 positive right justified Table 14. Serial Data Formats and Compatible DACs for the CS4202 Left Channel LRCK SCLK SDATA Left Channel LRCK SCLK SDATA LRCK ...
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... For further information on S/PDIF recommended transformers see application note AN134: AES and S/PDIF Recommended Transformers [4]. 7. EXCLUSIVE FUNCTIONS Some of the digital pins on the CS4202 have mul- tiplexed functionality. These functions are mutual- ly exclusive and cannot be requested at the same time. The following pairs of functions are mutually exclusive: • ...
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... This is done in accordance with the minimum timing specifications in the AC ’97 Seri- al Port Timing section on page 9. Once de-asserted, all of the CS4202 registers will be reset to their de- fault power-on states and the BIT_CLK and SDATA_IN signals will be reactivated. 8.1.2 ...
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... The PR[6:0] bits in this register control the internal powerdown states of the CS4202. Power- down control is available for individual subsections of the CS4202 by asserting any PRx bit or any com- bination of PRx bits. All powerdown states except PR4 and PR5 can be resumed by clearing the cor- responding PRx bit ...
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... Internal Clocks off (PR5) HP amp off (PR6) Digital off (PR4+PR5) All off (PR3+PR4+PR5) RESET Table 17. Power Consumption by Powerdown Mode for the CS4202 1 Assuming standard resistive load for transformer coupled coaxial S/PDIF output (Rload = 292 Ohm, DVdd = 3.3 V) (Rload = 415 Ohm, DVdd = 5 V). General HP_OUT_L, HP_OUT_R driving 4 Vpp into 32 Ohm resistive load ...
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... CLOCKING The CS4202 may be operated as a primary or sec- ondary codec primary codec, the system clock for the AC-link may be generated from an external 24.576 MHz clock source, a 24.576 MHz crystal, or the internal Phase Locked Loop (PLL). The PLL al- lows the CS4202 to accept external clock frequen- cies other than 24 ...
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... Primary Yes 1 0 Primary Yes 0 1 Primary Yes 0 0 Primary Primary Secondary Secondary Secondary Table 18. Clocking Configurations for the CS4202 DS549PP2 XTL_IN XTL_OUT Clock Codec Clock Rate ID Source (MHz) 0 External 24.576 0 External 14.31818 0 External 27.000 0 External 48.000 0 XTAL 24.576 1 BIT_CLK 12.288 ...
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... EMI reduction techniques refer to the application note AN165: CS4297A/CS4299 EMI Reduction Techniques [5]. 10.1 Analog Inputs All analog inputs to the CS4202, including CD_C, should be capacitively coupled to the input pins. Unused analog inputs should be tied together and connected through a capacitor to analog ground or tied to the Vrefout pin directly. The maximum al- ...
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... PC Beep Input The PC_BEEP input is useful for mixing the output of the “beeper” (timer chip), provided in most PCs, with the other audio signals. When the CS4202 is held in reset, PC_BEEP is passed directly to the line output. This allows the system sounds or “beeps” available before the AC ’ ...
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... AVdd2, supplies power to the AGND AGND headphone amplifier on the CS4202. The other ana- log power pin, AVdd1, supplies power to the rest of the CS4202 analog circuitry. The digital power pins, DVdd1 and DVdd2, should be connected to the same CS4202 DS549PP2 ...
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... AC-link interface. Since the digital interface on the CS4202 may oper- ate at either +3 proper connection of these pins will depend on the digital power supply of the controller. 10.5 Reference Design See Section 14 for a CS4202 reference design. DS549PP2 +12VD MC78M05CDT ...
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... GROUNDING AND LAYOUT Figure 26 on page 55 shows the conceptual layout for the CS4202 in XTAL or OSC clocking modes. The decoupling capacitors should be located phys- ically as close to the pins as possible. Also, note the connection of the REFFLT decoupling capacitors to the ground return trace connected directly to the ground return pin, AVss1 ...
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... Via to +5VA 0.1 µF Y5V AV ss2 DVdd1 Via to +5VD or +3.3VD Figure 26. Conceptual Layout for the CS4202 when in XTAL or OSC Clocking Modes DS549PP2 Vrefout toVia 1000 pF NPO AFLT1 AFLT2 REFFLT AVdd2 Via to Analog Ground Digital Ground Via to Digital Ground Pin 1 0.1 µF ...
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... PIN DESCRIPTIONS 36 MONO_OUT 37 AVdd2 38 HP_OUT_L 39 HP_OUT_C 40 HP_OUT_R 41 AVss2 42 GPIO0/LRCLK 43 GPIO1/SDOUT 44 ID0# 45 ID1# 46 EAPD/SCLK 47 SPDIF_OUT CS4202 48-pin Package Layout Figure 27. Pin Locations for the CS4202 CS4202 LINE_IN_R 23 LINE_IN_L 22 MIC2 21 MIC1 20 CD_R 19 CD_C 18 CD_L 17 VIDEO_R 16 VIDEO_L 15 AUX_R 14 AUX_L 13 PHONE DS549PP2 ...
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... AC-coupled to analog ground. CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20 These inputs form a stereo input pair to the CS4202 intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. ...
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... VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17 These inputs form a stereo input pair to the CS4202 intended to be used for the audio signal output of a video device. The maximum allowable input internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or AC-coupled to analog ground ...
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... SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8 This output signal transmits the status information and digital audio input streams from the ADCs. The data is clocked out of the CS4202 on the rising edge of BIT_CLK. A series terminating resistor of 47 Ω should be connected on this signal close to the CS4202. ...
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... Section 9, Clocking, for additional details. ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46 These pins select the Codec ID for the CS4202, as well as determine the rate of the incoming clock in PLL mode. They are only sampled after the rising edge of RESET#. These pins are internally pulled up to the digital supply voltage and should be left floating for logic ‘ ...
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... Power Supply Pins DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9 Digital supply voltage for the AC-link section of the CS4202. These pins can be tied digital or to +3.3 V digital. The CS4202 and controller’s AC-link should share a common digital supply. DVss1, DVss2 - Digital Ground, Pins 4 and 7 Digital ground connection for the AC-link section of the CS4202 ...
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... Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the CS4202. DAC Refers to a single Digital-to-Analog converter in the CS4202. “DACs” refers to the stereo pair of Digital-to-Analog converters. The CS4202 DACs have 20-bit resolution defined as dB relative to full-scale. The “A” indicates an A weighting filter was used. ...
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... SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS4202 operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 kHz. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level ...
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... REFERENCE DESIGN GND AVdd2 38 AVdd1 25 AVss2 42 AVss1 26 XTL_OUT XTL_IN DVdd1 1 DVdd2 9 GPIO3 33 CS4202 3 2 DS549PP2 ...
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... PC 2001 System Design Guide, Version 1.0, November 2000 http://www.pcdesguide.org/pc2001/default.htm ® 9) Intel 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub, June 1999 http://developer.intel.com/design/chipsets/datashts/290655.htm ® 10) Intel 82801BA (ICH2) I/O Controller Hub, October 2000 http://developer.intel.com/design/chipsets/datashts/290687.htm ® 11) Intel 82801CAM (ICH3-M) I/O Controller Hub, July 2001 http://developer.intel.com/design/chipsets/datashts/290716.htm DS549PP2 CS4202 65 ...
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... CS4202 A A1 MILLIMETERS MIN NOM MAX --- 1.40 0.05 0.10 0.17 0.22 8.70 9.0 BSC 6.90 7.0 BSC 8.70 9.0 BSC 6.90 7 ...