ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 94

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
Table 72. 10-Bit 525i YCrCb In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
Table 73. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
Table 74. 10-Bit 525i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
0x8A
Setting
0x02
0x1C
0x00
0x10
0xCB
0x10
0x0C
Setting
0x02
0x1C
0x00
0x10
0x10
0xC9
0x10
Setting
0x02
0x1C
0x00
0x10
0x10
0xC9
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Rev. B | Page 94 of 108
Table 75. 16-Bit 525i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
Table 76. 16-Bit 525i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
0x8A
Table 77. 16-Bit 525i RGB In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x87
0x88
0x8A
0x02
0x1C
0x00
0x10
0xC9
0x10
0x0C
0x02
0x1C
0x00
0x10
0x10
0xC9
0x10
0x0C
0x02
0x1C
0x00
0x10
0xC9
0x80
0x10
0x0C
Setting
Setting
Setting
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC / VSYNC
synchronization.
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.