ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 16

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
Y OUTPUT
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
SPECIFICATION SECTION OF THE DATA SHEET.
HSYNC
VSYNC
PIXEL PORT
PIXEL PORT
Y OUTPUT
SPECIFICATION SECTION OF THE DATA SHEET.
HSYNC
VSYNC
Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
b
b
Rev. B | Page 16 of 108
a
a
Cb0
Y0
Cb0
Cr0
Y1
Y0
Cb2
Y2
Cr0
Cr2
Y3
Y1