ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 28

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV739x via the MPU port, except for registers that are
specified as read-only or write-only registers.
The subaddress register determines the register accessed by the
next read or write operation. All communication through the
MPU port starts with an access to the subaddress register. A
read/write operation is then performed from/to the target
address, incrementing to the next address until the transaction
is complete.
Table 17. Register 0x00
SR7 to
SR0
0x00
Table 18. Register 0x01 to Register 0x09
SR7 to
SR0
0x01
Register
Power
mode
Register
Mode
select
Bit Description
Reserved.
DDR clock edge alignment
(used only for ED
DDR modes)
Reserved
Input mode
(see Subaddress 0x30, Bits[7:3]
for ED/HD standard selection)
Reserved
Bit Description
Sleep mode. With this control enabled, the current consumption is
reduced to μA level. All DACs and the internal PLL circuit are
disabled. Registers can be read from and written to in sleep mode.
PLL and oversampling control. This control allows the internal PLL
circuit to be powered down and the oversampling to be switched off.
DAC 3: power on/off.
DAC 2: power on/off.
DAC 1: power on/off.
Reserved.
2
and HD
7
0
6
0
0
0
0
1
1
1
1
Rev. B | Page 28 of 108
5
0
0
1
1
0
0
1
1
Bit Number
4
0
1
0
1
0
1
0
1
3
0
1
2
0
0
1
1
REGISTER PROGRAMMING
Table 17 to Table 34 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines which
register performs the next operation.
1
0
1
0
1
0
0
7
0
Register Setting
Chroma clocked in on rising clock edge and
luma clocked in on falling clock edge.
Reserved.
Reserved.
Luma clocked in on rising clock edge and
chroma clocked in on falling clock edge.
SD input.
ED/HD-SDR input.
ED/HD-DDR input.
Reserved.
Reserved.
Reserved.
Reserved.
ED (at 54 MHz) input.
6
0
5
0
Bit Number
4
0
1
3
0
1
3
2
0
1
1
0
1
0
0
1
Register
Setting
Sleep
mode off
Sleep
mode on
PLL on
PLL off
DAC 3 off
DAC 3 on
DAC 2 off
DAC 2 on
DAC 1 off
DAC 1 on
Reset
Value
0x12
Reset
Value
0x00