ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 100

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
Table 106. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 107. 16-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 108. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 109. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Setting
0x02
0x1C
0x10
0x10
0x1C
0x01
Setting
0x02
0x1C
0x10
0x10
0x18
0x01
Setting
0x02
0x1C
0x20
0x04
0x01
Setting
0x02
0x1C
0x20
0x04
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Rev. B | Page 100 of 108
Table 110. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 111. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 112. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 113. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
0x02
0x1C
0x20
0x10
0x04
0x01
0x02
0x1C
0x20
0x10
0x04
0x01
0x6C
0x02
0x1C
0x20
0x1C
0x01
0x02
0x1C
0x20
0x1C
0x01
0x6C
Setting
Setting
Setting
Setting
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.