ADUC7122BBCZ-RL Analog Devices Inc, ADUC7122BBCZ-RL Datasheet - Page 32
![PRECISION ANALOG MCU I.C](/photos/6/69/66991/bc-108-2_sml.jpg)
ADUC7122BBCZ-RL
Manufacturer Part Number
ADUC7122BBCZ-RL
Description
PRECISION ANALOG MCU I.C
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.ADUC7122BBCZ.pdf
(96 pages)
Specifications of ADUC7122BBCZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
41.78MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
126KB (63K x 16)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b, D/A 12x12b
Oscillator Type
Internal
Operating Temperature
-10°C ~ 95°C
Package / Case
108-LFBGA, CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADUC7122BBCZ-RL
ADUC7122BBCZ-RLTR
ADUC7122BBCZ-RLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADUC7122BBCZ-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADuC7122
Table 29. ADCCP MMR Bit Designations
(Address = 0xFFFF0504, Default Value = 0x00)
Bit
7:5
4:0
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
Others
Positive channel selection bits
ADC10/AINCM
Temperature sensor
Description
Reserved
PADC0P
PADC1P
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
Reserved
Reserved
Reserved
Reserved
Reserved
IOVDD_MON
Reserved
Reserved
V
AGND
Reserved
REF
Rev. 0 | Page 32 of 96
Table 30. ADCCN MMR Bit Designations
(Address = 0xFFFF0508, Default Value = 0x00)
Bit
7:5
4:0
Table 31. ADCSTA MMR Bit Designations
(Address = 0xFFFF050C, Default Value = 0x00)
Bit
0
0
Table 32. ADCDAT MMR Bit Designations
(Address = 0xFFFF0510, Default Value = 0x00000000)
Bit
27:16
Table 33. ADCRST MMR Bit Designations
(Address = 0xFFFF0514, Default Value = 0x00)
Bit
0
Table 34. PGA_GN MMR Bit Designations
(Address = 0xFFFF0520, Default Value = 0x0000)
Bit
15:12
11:6
5:0
Note that PGA_PADC0_GN and PGA_PADC1_GN must be ≤32.
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
Others
Value
1
0
Value
1
Value
Value
Description
Indicates that an ADC conversion is complete.
It is set automatically when an ADC conversion
completes.
Automatically cleared by reading the ADCDAT
MMR.
Description
Holds the ADC result (see Figure 15).
Description
Set to 1 by the user to reset all the ADC
registers to their default values.
Reserved. Set to 0.
Gain of PGA for PADC1 (PGA_PADC1_GN)
Description
Gain of PGA for PADC0 (PGA_PADC0_GN)
= 1 + 4 × (PGA_ADC0_GN/32)
= 1 + 4 × (PGA_ADC1_GN/32)
Description
Reserved
Negative channel selection bits
PADC0N
PADC1N
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10/AINCM
Reserved
AGND
Reserved
IOGND
Reserved