ADUC7061BCPZ32-RL Analog Devices Inc, ADUC7061BCPZ32-RL Datasheet - Page 25

• Manufacturer Part Number: ADUC7061BCPZ32-RL
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7061BCPZ32-RL

• Design Resources: USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FEEDAT Register
FEEDAT is a 16-bit data register. This register holds the data
value for flash read and write commands.
Name:
Address:
Default value:
Access:
FEEADR Register
FEEADR is a 16-bit address register used for accessing
individual pages of the 32 kB flash block. The valid address
range for a user is: 0x0000 to 0x77FF. This represents the 30 kB
flash user memory space. A read or write access outside this
boundary causes a data abort exception to occur.
Name:
Address:
Default value:
Access:
FEESIGN Register
The FEESIGN register is a 24-bit MMR. This register is updated
with the 24-bit signature value after the signature command is
executed. This value is the result of the linear feedback shift
register (LFSR) operation initiated by the signature command.
Name:
Address:
Default value:
Access:
FEEPRO Register
The FEEPRO MMR provides protection following a subsequent
reset of the MMR. It requires a software key (see Table 16).
Name:
Address:
Default value:
Access:
FEEDAT
0xFFFF0E0C
0xXXXX
Read and write
FEEADR
0xFFFF0E10
0x0000
Read and write
FEESIGN
0xFFFF0E18
0xFFFFFF
Read
FEEPRO
0xFFFF0E1C
0x00000000
Read and write
Rev. B | Page 25 of 108
FEEHIDE Register
The FEEHIDE MMR provides immediate protection. It does
not require any software key. Note that the protection settings
in FEEHIDE are cleared by a reset (see Table 16).
Name:
Address:
Default value:
Access:
Table 16. FEEPRO and FEEHIDE MMR Bit Designations
Bit
31
30
29
28:0
Command Sequence for Executing a Mass Erase
FEEDAT = 0x3CFF;
FEEADR = 0x77C3;
FEEMOD = FEEMOD|0x8;
FEECON = 0x06;
Description
Read protection.
Cleared by user to protect all code. No JTAG read
accesses for protected pages if this bit is cleared.
Set by the user to allow reading the code via JTAG.
Protection for Page 59 (0x00087600 to 0x000877FF).
Set by the user to allow writing to Page 59. Cleared to
protect Page 59.
Protection for Page 58 (0x00087400 to 0x000875FF).
Set by the user to allow writing to Page 58. Cleared to
protect Page 58.
Write protection for Page 57 to Page 0. Each bit
represents two pages. Each page is 512 bytes in size.
Bit 0 is protection for Page 0 and Page 1 (0x00080000
to 0x000803FF). Set by the user to allow writing Page 0
and Page 1. Cleared to protect Page 0 and Page 1.
Bit 1 is protection for Page 2 and Page 3 (0x00080400
to 0x000807FF. Set by the user to allow writing Page 2
and Page 3. Cleared to protect Page 2 and Page 3.
…
…
Bit 27 is protection for Page 54 and Page 55
(0x00087000 to 0x000873FF). Set by the user to allow
writing to Page 54 and Page 55. Cleared to protect
Page 54 and Page 55.
Bit 28 is protection for Page 56 and Page 57
(0x00087400 to 0x000877FF). Set by the user to allow
writing to Page 56 and Page 57. Cleared to protect
Page 56 and Page 57.
ADuC7060/ADuC7061
//Erase key enable
//Mass erase command
FEEHIDE
0xFFFF0E20
0xFFFFFFFF
Read and write