ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 6

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
3.
4.
5.
05000105 - Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match:
05000119 - DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops:
05000122 - Rx.H Cannot Be Used to Access 16-bit System MMR Registers:
DESCRIPTION:
Even when the Watchpoint Data Address Counters (WPDACTL:WPDCNTENx) are enabled, the corresponding Watchpoint Status Register
bits (WPSTAT:STATDAx) will be set on every match, not just on the expiration of the counter.
The same is true for the Watchpoint Instruction Address Counters (WPIACTL:WPICNTENx) and Status Bits (WPSTAT:STATIAx).
WORKAROUND:
When a watchpoint interrupt occurs, you must validate the set WPSTAT bits with their counter enable bits and counter register values
(WPIACNTn or WPDACTn).
Note: Because the Counter Register only decrements to 0x0000, its value will equal 0x0000 when the counter has expired AND when it is 1
match away from its counter expiring.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
DESCRIPTION:
After completion of a Peripheral Receive DMA, the DMAx_IRQ_STATUS:DMA_RUN bit will be in an undefined state.
WORKAROUND:
The DMA interrupt and/or the DMAx_IRQ_STATUS:DMA_DONE bits should be used to determine when the channel has completed
running.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
DESCRIPTION:
When accessing 16-bit system MMR registers, the high half of the data registers may not be used. If a high half register is used, incorrect
data will be written to the system MMR register, but no exception will be generated. For example (where P0 points to a 16-bit system
MMR), this access would fail:
WORKAROUND:
Use other forms of 16-bit transfers when accessing 16-bit system MMR registers. For example (where p0 points to a 16-bit system MMR):
The VisualDSP++ Blackfin compiler will not normally emit a problem instruction when generating code. It will insert a pack instruction to
swap register halves in the cases where the MMR load occurs with a constant address, e.g. *MMR_Reg = value; It cannot, however,
identify pointers unknown at compile time (such as parameters to functions) as pointers to MMRs. The VisualDSP++ runtime libraries also
avoid this anomaly.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
w[P0] = R5.H;
w[p0] = r5.l;
r4.l = w[p0];
r3 = w[p0](z);
w[p0] = r3;
NR003532D | Page 6 of 45 | July 2008
Silicon Anomaly List