ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 42

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
73.
74.
DESCRIPTION:
When a Break signal is received, the UART controller should issue a single error interrupt. However, the controller issues a number of error
interrupts instead, as it generates an error interrupt for every bit time that the break signal is active. For example, if a break signal holds
the line low for ~250ms at a baud rate of 57600. This results in ~1400 error interrupts being generated, independent of the fact that there
is no start or stop bits in the stream. Internally, the data is received as 0s in the UART_RBR register, as the data sampled is all 0s during the
break signal.
Another problem with the above is the timing of the break signal itself. Depending on when the next valid character is transmitted, the
result of the Break signal may split the next valid character into two invalid characters, as the first bits received may be appended to the
previous bad data, with the rest of the valid character sampled as the NEXT character. This behavior can propogate through a stream of
subsequent characters received over the UART if data is continuously streamed after a break.
WORKAROUND:
For the flood of interrupts generated by the single break signal, there is no workaround other than to have software condense the
numerous interrupts into one and then service it. Every error interrupt that is generated must be serviced individually. For example,
software could use a flag to control this. If the UART error interrupt handler sets a flag and then skips subsequent interrupt requests until
that flag is cleared, the multiple breaks can be treated as one. The same flag would be cleared in the UART RX interrupt to indicate that
the break has completed and new valid data has been received over the UART.
For the data being split after the break concludes, that data will be unrecoverable. If the host holds off on sending the next data after the
break for one full character's worth of bit times, the Blackfin UART will have recovered from the break signal and will be ready to resume
receiving valid data. For example, for 8-bit data with a start bit, a parity bit, and two stop bits, the host should wait at least 12 UART bit
times after a break signal before issuing the next valid data.
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
If the PPI port is configured in ITU-R 656 Output Mode, the FIFO Underrun bit (UNDR in PPI_STATUS) does not get set when a PPI FIFO
underrun occurs. An underrun can happen due to limited bandwidth or the PPI DMA failing to gain access to the bus due to arbitration
latencies.
WORKAROUND:
None.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
05000363 - UART Break Signal Issues:
05000366 - PPI Underflow Error Goes Undetected in ITU-R 656 Mode:
NR003532D | Page 42 of 45 | July 2008
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