ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 39

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
68.
DESCRIPTION:
When instruction cache is enabled, invalid code may be executed when any of the following instructions are interrupted:
• CSYNC
• SSYNC
• LCx =
• LTx = (only when LCx is non-zero)
• LBx = (only when LCx is non-zero)
When this problem occurs, a variety of incorrect things could happen, including an illegal instruction exception. Additional errors could
show up as an exception, a hardware error, or an instruction that is valid but different than the one that was expected.
WORKAROUND:
Place a cli before all SSYNC, CSYNC, "LCx =", "LTx =", and "LBx =" instructions to disable interrupts, and place an sti after each of
these instructions to re-enable interrupts. When these instructions are executed in code that is already non-interruptible, the problem will
not occur.
In an interrupt service routine that will enable interrupt nesting, be sure to push the LCx, LTx, and LBx registers before pushing RETI,
which enables interrupt nesting. Following the inverse during the ISR context restore will guarantee that RETI is popped before the loop
registers are loaded, thus disabling nested interrupts and protecting the loads from this anomaly situation. For example:
Finally, as the workaround involves Supervisor Mode instructions to disable and enable interrupts, this does not apply to User Mode. In
user space, do not use CSYNC or SSYNC instructions. Also, do not load the loop registers directly. Instead, utilize hardware loops which
can be implemented with the LSETUP instruction, which limits loop ranges to 2046 bytes.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
05000312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted:
INT_HANDLER:
[--sp] = astat;
[--sp] = lc0; // push loop registers before pushing RETI
[--sp] = lt0;
[--sp] = lb0;
[--sp] = lc1;
[--sp] = lt1;
[--sp] = lb1;
[--sp] = reti; // push RETI to enable nested interrupts
[--sp] = ...
...
reti = [sp++]; // pop RETI to disable interrupts
lb1 = [sp++];
lt1 = [sp++];
lc1 = [sp++];
lb0 = [sp++];
lt0 = [sp++];
lc0 = [sp++];
astat = [sp++];
// body of interrupt handler
= [sp++];
// it is now safe to load the loop registers
NR003532D | Page 39 of 45 | July 2008
ADSP-BF531/BF532/BF533