ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 28

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
49.
DESCRIPTION:
A noisy board environment combined with slow input edge rates on external SPORT receive (RSCLK) and transmit clocks (TSCLK) may
cause a variety of observable problems. Spurious high frequency transitions on the RSCLK/TSCLK can cause the SPORT to recognize an
extra noise-induced glitch clock pulse.
The high frequency transitions on the RSCLK/TSCLK are most likely to be caused by noise on the rising or falling edge of external serial
clocks. This noise, coupled with a slowly transitioning serial clock signal, can cause an additional bit-clock with a short period due to high
sensitivity of the clock input. A slow slew rate input allows any noise on the clock input around the switching point to cause the clock
input to cross and re-cross the switching point. This oscillation can cause a glitch clock pulse in the internal logic of the serial port.
Problems which may be observed due to this glitch clock pulse are:
• In stereo serial modes, this will show up as missed frame syncs, causing left/right data swaps.
• In multichannel mode, this will show up as MFD counts appearing inaccurate or skipped frames.
• In Normal (Early) Frame sync mode, data words received will be shifted right one bit. The MSB may be incorrectly captured in sign
extension mode.
• In any mode, received or transmitted data words may appear to be partially right shifted if noise occurs on any input clocks between the
start of frame sync and the last bit to be received or transmitted.
In Stereo Serial mode (bit 9 set in SPORTx_RCR2), spurious high frequency transitions on RSCLK/TSCLK can cause the SPORT to miss rising
or falling edges of the word clock. This causes left or right words of Stereo Serial data to be lost. This may be observed as a Left/Right
channel swap when listening to stereo audio signals. The additional noise-induced bit-clock pulse on the SPORT's internal logic results in
the FS edge-detection logic generating a pulse with a smaller width and, at the same time, prevents the SPORT from detecting the
external FS signal during the next ‘normal' bit-clock period. The FS pulse with smaller width, which is the output of the edge-detection
logic, is ignored by the SPORT's sequential logic. Due to the fact that the edge detection part of the FS-logic was already ‘triggered', the
next ‘normal' RSCLK will not detect the change in RFS anymore. In I2S/EIAJ mode, this results in one stereo sample being
detected/transferred as two left/right channels, and all subsequent channels will be word-swapped in memory.
In multichannel mode, the mutlichannel frame delay (MFD) logic receives the extra sync pulse and begins counting early or double
counting (if the count has already begun). A MFD of zero can roll over to 15, as the count begins one cycle early.
In early frame sync mode, if the noise occurs on the driving edge of the clock the same cycle that FS becomes active, the FS logic receives
the extra runt pulse and begins counting the word length one cycle early. The first bit will be sampled twice and the last bit will be
skipped.
In all modes, if the noise occurs in any cycle after the FS becomes active, the bit counting logic receives the extra runt pulse and advances
too rapidly. If this occurs once during a work unit, it will finish counting the word length one cycle early. The bit where the noise occurs
will be sampled twice, and the last bit will be skipped.
WORKAROUND:
1) Decrease the sensitivity to noise by increasing the slew rate of the bit clock or make the rise and fall times of serial bit clocks short, such
that any noise around the transition produces a short duration noise-induced bit-clock pulse. This small high-frequency pulse will not
have any impact on the SPORT or on the detection of the frame-sync. Sharpen edges as much as possible, if this is suitable and within EMI
requirements.
2) If possible, use internally generated bit-clocks and frame-syncs.
3) Follow good PCB design practices. Shield RSCLK with respect to TSCLK lines to minimize coupling between the serial clocks.
4) Separate RSCLK, TSCLK, and Frame Sync traces on the board to minimize coupling which occurs at the driving edge when FS switches.
A specific workaround for problems observed in Stereo Serial mode is to delay the frame-sync signal such that noise-induced bit-clock
pulses do not start processing the frame-sync. This can be achieved if there is a larger serial resistor in the frame-sync trace than the one in
the bit-clock trace. Frame-sync transitions should not cross the 50% point until the bit-clock crosses the 10% of VDD threshold (for a
falling edge bit-clock) or the 90% threshold (for a rising edge bit-clock).
To improve immunity to noise, newer silicon revisions implement optional hysteresis that can be enabled for input pins by setting bit 15
of the PLL_CTL register, followed by the appropriate PLL programming sequence.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
05000265 - Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks:
NR003532D | Page 28 of 45 | July 2008
Silicon Anomaly List