ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 36

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
63.
64.
DESCRIPTION:
When a DMA channel has been granted permission to fetch descriptors from memory, writes to System MMRs associated with the same
DMA controller will be held off until the descriptor fetch completes, regardless of the presence of an SSYNC instruction.
One unwanted effect from this behavior would be in the case of DMA interrupts, where the ISR code performs the correct sequence to
clear the interrupt request:
If another DMA channel from the same DMA controller is currently fetching descriptors at the time of the write, this write will be delayed
and, if the delay exceeds the duration of the subsequent SSYNC instruction, the ISR code will execute the RTI instruction and vector to the
ISR again because the DMAx_IRQ_STATUS bit hasn't yet been cleared. This behavior is true for writes to all system MMRs associated with
the DMA Controller that is busy doing the descriptor fetch.
WORKAROUND:
If a dummy read from the MMR register is inserted before the SSYNC, this will guarantee that the previous write completes before the
read is able to execute. For example, using the above example, read back the IRQ Status register after it is written:
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
The SPORT Hysteresis bit (SPORT_HYS, bit 15) in the PLL_CTL register is not functional. This bit always reads as 0, and writing a 1 has no
effect.
WORKAROUND:
None.
APPLIES TO REVISION(S):
0.3, 0.4
05000302 - SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly:
05000305 - SPORT_HYS Bit in PLL_CTL Register Is Not Functional:
p0.h = hi(DMA3_IRQ_STATUS);
p0.l = lo(DMA3_IRQ_STATUS);
r0.l = 0x0001;
w[p0] = r0.l;
ssync;
rti;
p0.h = hi(DMA3_IRQ_STATUS);
p0.l = lo(DMA3_IRQ_STATUS);
r0.l = 0x0001;
w[p0] = r0.l;
r0.l = w[p0];
ssync;
rti;
// Write-1-to-Clear Interrupt Request
// Allow write to complete
// Write-1-to-Clear Interrupt Request
// Insert dummy read before ssync
// Allow write to complete
NR003532D | Page 36 of 45 | July 2008
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