ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 23

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
42.
DESCRIPTION:
Unpredictable behavior can result when hardware loops shorter than 4 instructions in length are interrupted at the end of the loop due to
an interrupt or exception. In this situation, the processor's loop buffers, which are used to reduce the instruction fetch latency, operate
incorrectly, resulting in the wrong instructions being fetched as the loop exits.
WORKAROUND:
There are a few possible workarounds for this anomaly. The first is to clear the loop buffers by writing to the Loop Counter registers (LC0
and LC1) inside all interrupt/exception handlers:
A second idea would be to include the loop counters in the context switch code:
Finally, another workaround would be to pad the loop with NOPs to increase the loop length to greater than or equal to 4 instructions.
Alternatively, if the event handlers use hardware loops, the above steps are not required, since every time an LCx register is written to, its
corresponding loop buffer is cleared.
The VisualDSP++ Blackfin Compiler includes a workaround for this anomaly. The compiler will automatically enable the workaround for
the appropriate silicon revisions and part numbers, or you can enable the workaround manually by specifying the compiler flag ‘-
workaround short-loop-exceptions-257'. With the workaround enabled, the compiler will include a save and restore of the LC0 and LC1
registers in interrupt and exception handlers when this is not already performed. The compiler would normally only save these registers if
they were used within the handler routine.
The macro __WORKAROUND_SHORT_LOOP_EXCEPTIONS will be defined at compile, assemble and link build phases when the
workaround is enabled.
APPLIES TO REVISION(S):
0.3, 0.4
05000257 - Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches:
R0=LC0;
LC0=R0;
R0=LC1;
LC1=R0;
[--SP] = LC0;
[--SP] = LC1;
<interrupt code>
LC1 = [SP++];
LC0 = [SP++];
NR003532D | Page 23 of 45 | July 2008
ADSP-BF531/BF532/BF533