ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 9
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ADSP-BF514BBCZ-4F4
Manufacturer Part Number
ADSP-BF514BBCZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514BBCZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514BBCZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
168-LFBGA
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Package
168CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
400 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
AD
Quantity:
204
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three signals have a programmable debouncing
circuit.
An internal signal forwarded to the GP timer unit enables one
timer to measure the intervals between count events. Boundary
registers enable auto-zero operation or simple system warning
by interrupts when programmable count values are exceeded.
Serial Ports
The ADSP-BF51x processors incorporate two dual-channel syn-
chronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configura-
tion, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
Serial ports operate in five modes:
Serial Peripheral Interface (SPI) Ports
The processors have two SPI-compatible ports (SPI0 and SPI1)
that enable the processor to communicate with multiple SPI-
compatible devices.
The SPI interface uses three signals for transferring data: two
data signals (master output-slave input–MOSI, and master
input-slave output–MISO) and a clock signal (serial
clock–SCK). An SPI chip select input signal (SPIxSS) lets other
SPI devices select the processor, and multiple SPI chip select
output signals let the processor select other SPI devices. The SPI
select signals are reconfigured general-purpose I/O signals.
Using these signals, the SPI port provides a full-duplex, syn-
chronous serial interface, which supports both master/slave
modes and multimaster environments.
The SPI port baud rate and clock phase/polarities are program-
mable, and it has an integrated DMA channel, configurable to
support transmit or receive data streams. The SPI’s DMA chan-
nel can only service unidirectional accesses at any given time.
UART Ports
The processors provide two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
and none, even, or odd parity. Optionally, an additional address
• Standard DSP serial mode
• Multichannel (TDM) mode
• I
• Packed I
• Left-justified mode
2
S mode
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
2
S mode
Rev. B | Page 9 of 68 | January 2011
bit can be transferred to interrupt only addressed nodes in
multi-drop bus (MDB) systems. A frame is terminates by one,
one and a half, two or two and a half stop bits.
The UART ports support automatic hardware flow control
through the Clear To Send (CTS) input and Request To Send
(RTS) output with programmable assertion FIFO levels.
To help support the Local Interconnect Network (LIN) proto-
cols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable inter-frame space.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
2-Wire Interface (TWI)
The processors include a TWI module for providing a simple
exchange method of control data between multiple devices. The
TWI is compatible with the widely used I
TWI module offers the capabilities of simultaneous master and
slave operation, support for both 7-bit addressing and multime-
dia data arbitration. The TWI interface utilizes two signals for
transferring clock (SCL) and data (SDA) and supports the pro-
tocol at speeds up to 400k bits/sec. The TWI interface signals
are compatible with 5 V logic levels.
Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices.
Removable Storage Interface (RSI)
The RSI controller, available on the ADSP-BF514, ADSP-
BF516, ADSP-BF518, and ADSP-BF518F acts as the host inter-
face for multi-media cards (MMC), secure digital memory cards
(SD Card), secure digital input/output cards (SDIO), and CE-
ATA hard disk drives. The following list describes the main fea-
tures of the RSI controller.
• Support for a single MMC, SD memory, SDIO card or CE-
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit and 8-bit MMC modes
• Support for 4-bit and 8-bit CE-ATA hard disk drives
• A ten-signal external interface with clock, command, and
• Card detection using one of the data signals
• Card interface clock generation from SCLK
• SDIO interrupt and read wait features
• CE-ATA command completion signal recognition and
ATA hard disk drive
up to eight data lines
disable
2
C
®
bus standard. The