ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 31
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ADSP-BF514BBCZ-4F4
Manufacturer Part Number
ADSP-BF514BBCZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514BBCZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514BBCZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
168-LFBGA
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Package
168CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
400 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
AD
Quantity:
204
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
SDRAM Interface Timing
Table 28. SDRAM Interface Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
The t
Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
SSDAT
HSDAT
SCLK
SCLKH
SCLKL
DCAD
HCAD
DSDAT
ENSDAT
SCLK
value is the inverse of the f
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Data Setup Before CLKOUT
Data Hold After CLKOUT
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
Command, Address, Data Delay After CLKOUT
Command, Address, Data Hold After CLKOUT
Data Disable After CLKOUT
Data Enable After CLKOUT
DATA (OUT)
COMMAND,
ADDRESS
DATA (IN)
CLKOUT
(OUT)
1
SCLK
specification discussed in
NOTE: COMMAND =
t
SSDAT
Rev. B | Page 31 of 68 | January 2011
Table 11 on Page
Figure 12. SDRAM Interface Timing
2
2
t
DCAD
,
t
HSDAT
t
SCLK
21. Package type and reduced supply voltages affect the best-case value listed here.
,
t
ENSDAT
, SDQM,
12.5
Min
1.5
1.3
5
5
1
0
1.8V Nominal
t
DCAD
t
, SA10, SCKE.
HCAD
V
DDMEM
t
SCLKL
Max
t
5.5
HCAD
5
t
SCLKH
t
DSDAT
2.5 V/3.3V Nominal
Min
1.5
0.8
10
4
4
1
0
V
DDMEM
Max
4
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns