ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 41
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
ADSP-BF514BBCZ-4F4
Manufacturer Part Number
ADSP-BF514BBCZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514BBCZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514BBCZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
168-LFBGA
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Package
168CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
400 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
AD
Quantity:
204
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Serial Peripheral Interface (SPI) Port—Master Timing
Table 37
Table 37. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
SSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
HSPIDM
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
and
CPHA = 1
CPHA = 0
Figure 25
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISELx low to First SCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
(OUTPUT)
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
SPIxMOSI
(OUTPUT)
SPIxMISO
SPIxSCK
(INPUT)
(INPUT)
describe SPI port master operations.
t
SSPIDM
t
SDSCIM
t
HSPIDM
t
SPICLM
Figure 25. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. B | Page 41 of 68 | January 2011
t
SPICHM
t
HDSPIDM
t
HDSPIDM
Min
11.6
–1.5
2 × t
2 × t
2 × t
4 × t
2 × t
2 × t
–1
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
1.8V Nominal
DDSPIDM
–1.5
–1.5
–1.5
–1.5
–1.5
t
V
SPICLK
t
DDSPIDM
DDEXT
Max
6
t
SSPIDM
t
HDSM
–1
Min
9.6
–1.5
2 × t
2 × t
2 × t
4 × t
2 × t
2 × t
t
HSPIDM
2.5 V/3.3V Nominal
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
–1.5
–1.5
–1.5
–1.5
–1.5
t
V
SPITDM
DDEXT
Max
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns