ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 32
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ADSP-BF514BBCZ-4F4
Manufacturer Part Number
ADSP-BF514BBCZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514BBCZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514BBCZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
168-LFBGA
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Package
168CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
400 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
AD
Quantity:
204
Company:
Part Number:
ADSP-BF514BBCZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
External DMA Request Timing
Table 29
operations.
Table 29. External DMA Request Timing
1
Parameter
Timing PRequirements
t
t
t
t
Because the external DMA control pins are part of the V
DR
DH
DMARACT
DMARINACT
V
DDMEM
are NOT equal may require level shifting logic for correct operation.
and
Figure 13
DMARx Asserted to CLKOUT High Setup
CLKOUT High to DMARx Deasserted Hold Time
DMARx Active Pulse Width
DMARx Inactive Pulse Width
(ACTIVE HIGH)
(ACTIVE LOW)
DMAR0/1
CLKOUT
describe the External DMA Request
t
DS
1
DDEXT
t
DMARACT
power domain and the CLKOUT signal is part of the V
Rev. B | Page 32 of 68 | January 2011
Figure 13. External DMA Request Timing
t
DH
Min
9
0
t
1.75 × t
SCLK
t
DMARINACT
+ 1
1.8 V Nominal
V
SCLK
DDMEM
/V
Max
DDEXT
DDMEM
power domain, systems in which V
Min
7.2
0
t
1.75 × t
SCLK
2.5 V/3.3 V Nominal
+ 1
V
SCLK
DDMEM
/V
Max
DDEXT
DDEXT
Unit
ns
ns
ns
ns
and