ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 37

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

Three-State Timing—Bus Master, Bus Slave
See
memory interface is disabled (stops driving) or enabled
(resumes driving) relative to CLKIN and the SBTS pin. This
timing is applicable to bus master transition cycles (BTC) and
host transition cycles (HTC) as well as the SBTS pin.
Table 25. Three-State Timing—Bus Master, Bus Slave
1
2
3
4
5
6
7
8
9
10
11
12
13
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
For ADSP-21160M, specification is 1 ns, minimum.
Strobes = RDx, WRx, and DMAGx.
For ADSP-21160M, specification is 0.25t
If access aborted by SBTS, then strobes disable before CLKIN [0.25t
For ADSP-21160M, specification is 0.25t
For ADSP-21160M, specification is 3.5 ns (minimum).
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
For ADSP-21160M, specification is 1.5 ns (minimum) and 10 ns (maximum).
For ADSP-21160M, specification is 1.5 ns (minimum).
For ADSP-21160M, specification is 0.5 ns (minimum).
Not specified for ADSP-21160M.
Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).
For ADSP-21160M, specification is t
STSCK
HTSCK
MIENA
MIENS
MIENHG
MITRA
MITRS
MITRHG
DATEN
DATTR
ACKEN
ACKTR
CDCEN
CDCTR
ATRHBG
STRHBG
PTRHBG
BTRHBG
MENHBG
Table 25
and
SBTS Setup Before CLKIN
SBTS Hold After CLKIN
Address/Select Enable After CLKIN
Strobes Enable After CLKIN
HBG Enable After CLKIN
Address/Select Disable After CLKIN
Strobes Disable After CLKIN
HBG Disable After CLKIN
Data Enable After CLKIN
Data Disable After CLKIN
ACK Enable After CLKIN
ACK Disable After CLKIN
CLKOUT Enable After CLKIN
CLKOUT Disable After CLKIN
Address, MSx Disable Before HBG Low
RDx, WRx, DMAGx Disable Before HBG Low
Page Disable Before HBG Low
BMS Disable Before HBG Low
Memory Interface Enable After HBG High
Figure
22. These specifications show how the
CK
+5 ns (maximum).
CCLK
CCLK
1
–1 ns (minimum) and 0.25t
ns (maximum).
7
7, 8
7
6
7, 9
2
2, 4, 5
10
11
11
3
Rev. B | Page 37 of 60 | February 2010
11
CCLK
12, 13
11
+ 1.5 (min.), 0.25t
CCLK
+4 ns (maximum).
Min
6
2
1.5
1.5
1.5
0.5
0.25t
0.5
0.25t
0.5
1.5
1.5
0.5
t
1.5t
t
t
0.5t
t
CCLK
CK
CK
CK
CCLK
+ 0.25t
– 6
– 5
CK
CK
– 3
CCLK
CCLK
– 6
– 6.5
+ 5 (max.)]
– 4
+1
CCLK
– 6
ADSP-21160M/ADSP-21160N
Max
9
9
9
9
0.25t
8
0.25t
5
9
5
9
t
1.5t
t
t
0.5t
t
CCLK
CK
CK
CK
+6
+ 0.25t
+ 5
CK
CK
+1
CCLK
CCLK
+ 5
+ 1.5
+1.5
+ 7
CCLK
+ 5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns