ADCLK854/PCBZ Analog Devices Inc, ADCLK854/PCBZ Datasheet - Page 7

• Manufacturer Part Number: ADCLK854/PCBZ
• Description: Evaluation Kit For 1.8v 6vvds/12 CMOS Cl
• Manufacturer: Analog Devices Inc

Specifications of ADCLK854/PCBZ

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Main Purpose: Timing, Clock Buffer / Driver / Receiver / Translator
• Embedded: No
• Utilized Ic / Part: ADCLK854
• Primary Attributes: 2 Inputs, 12 Outputs
• Secondary Attributes: CMOS, LVDS Outputs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
7, 18, 24, 30,
37, 43
5
6
8
9
10
11
12
13
14
15
16
4, 17, 23, 29,
38, 44
19
20
21
22
25
Mnemonic
V
CLK0
CLK0
V
CLK1
CLK1
OUT11 (OUT11B)
OUT11 (OUT11A)
IN_SEL
CTRL_A
CTRL_B
CTRL_C
SLEEP
OUT10 (OUT10B)
OUT10 (OUT10A)
GND
OUT9 (OUT9B)
OUT9 (OUT9A)
OUT8 (OUT8B)
OUT8 (OUT8A)
OUT7 (OUT7B)
REF
S
Description
Reference Voltage.
Input (Negative) 0.
Input (Positive) 0.
Supply Voltage.
Input (Negative) 1.
Input (Positive) 1.
Complementary Side of Differential LVDS Output 11, or CMOS Output 11 on Channel B.
True Side of Differential LVDS Output 11, or CMOS Output 11 on Channel A.
Input Select. (0 = CLK0, CLK0 ; 1 = CLK1, CLK1 ). CMOS logic input with 200 kΩ pull-down resistor.
Control for Output 3 to Output 0 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor.
Control for Output 7 to Output 4 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor.
Control for Output 11 to Output 8 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor.
Sleep Mode Control (0 = normal operation, 1 = sleep). CMOS logic input with 200 kΩ pull down resistor.
Complementary Side of Differential LVDS Output 10, or CMOS Output 10 on Channel B.
True Side of Differential LVDS Output 10, or CMOS Output 10 on Channel A.
Ground Pin.
Complementary Side of Differential LVDS Output 9, or CMOS Output 9 on Channel B.
True Side of Differential LVDS Output 9, or CMOS Output 9 on Channel A.
Complementary Side of Differential LVDS Output 8, or CMOS Output 8 on Channel B.
True Side of Differential LVDS Output 8, or CMOS Output 8 on Channel A.
Complementary Side of Differential LVDS Output 7, or CMOS Output 7 on Channel B.
OUT11 (OUT11B)
OUT11 (OUT11A)
CTRL_A
CTRL_B
IN_SEL
CLK0
CLK0
CLK1
CLK1
V
GND
REF
V
S
NOTES:
1. NC = NO CONNECT.
2. EXPOSED PADDLE MUST BE CONNECTED TO GND.
10
11
12
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 2. Pin Configuration
Rev. 0 | Page 7 of 16
ADCLK854
(Not to Scale)
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
V
GND
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
S
ADCLK854