ADCLK854/PCBZ Analog Devices Inc, ADCLK854/PCBZ Datasheet - Page 3

• Manufacturer Part Number: ADCLK854/PCBZ
• Description: Evaluation Kit For 1.8v 6vvds/12 CMOS Cl
• Manufacturer: Analog Devices Inc

Specifications of ADCLK854/PCBZ

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Main Purpose: Timing, Clock Buffer / Driver / Receiver / Translator
• Embedded: No
• Utilized Ic / Part: ADCLK854
• Primary Attributes: 2 Inputs, 12 Outputs
• Secondary Attributes: CMOS, LVDS Outputs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ) values are given for V
the full V
Table 1. Clock Inputs and Outputs
Parameter
CLOCK INPUTS
Input Sensitivity, Single-Ended
LVDS CLOCK OUTPUTS
CMOS CLOCK OUTPUTS
Input Frequency
Input Sensitivity, Differential
Input Level
Input Common-Mode Voltage
Input Common-Mode Range
Input Voltage Offset
Input Resistance (Differential)
Input Capacitance
Input Bias Current (Each Pin)
Output Frequency
Output Voltage Differential
Offset Voltage
Short-Circuit Current
Output Frequency
Output Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Reference Voltage
Delta V
Delta V
Output Voltage
Output Resistance
Output Current
S
= 1.8 V ± 5% and T
OD
OS
A
= −40°C to +85°C variation, unless otherwise noted. Input slew rate > 1 V/ns, unless otherwise noted.
S
= 1.8 V and T
Symbol
V
V
C
V
ΔV
V
ΔV
I
V
V
V
V
V
S
A, I
CM
CMR
IN
OD
OS
OH
OL
OH
OL
REF
OD
OS
S
B
Min
0
V
0.4
−350
247
1.125
V
V
V
S
S
S
S
A
/2 − 0.1
/2 − 0.1
− 0.1
− 0.35
= 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are given over
150
Typ
30
150
7
2
344
1.25
3
V
60
S
/2
Rev. 0 | Page 3 of 16
Max
1200
1.8
V
V
+350
1200
454
50
1.375
50
6
250
0.1
0.35
V
500
S
S
S
/2 + 0.5
/2 + 0.1
− 0.4
Unit
MHz
mV p-p
V p-p
V
V
mV
mV p-p
kΩ
pF
μA
MHz
mV
mV
V
mV
mA
MHz
V
V
V
V
V
Ω
μA
Conditions
Differential input
Jitter performance improves with higher slew
rates (greater voltage swing)
Larger voltage swings can turn on the protection
diodes and degrade jitter performance
Inputs are self-biased; enables ac coupling
Inputs dc-coupled with 200 mV p-p signal applied
CLKx ac-coupled; CLKx ac bypassed to ground
Full input swing
Termination = 100 Ω; differential (OUTx, OUTx )
See Figure 9 for swing vs. frequency
Each pin (output shorted to GND)
Single-ended; termination = open; OUTx and
OUTx in phase
swing vs. frequency
@ 1 mA load
@ 1 mA load
@ 10 mA load
@ 10 mA load
±500 μA
With 10 pF load per output; see Figure 16 for
ADCLK854