ADCLK854/PCBZ Analog Devices Inc, ADCLK854/PCBZ Datasheet

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ADCLK854/PCBZ

Manufacturer Part Number
ADCLK854/PCBZ
Description
Evaluation Kit For 1.8v 6vvds/12 CMOS Cl
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADCLK854/PCBZ

Design Resources
Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
Main Purpose
Timing, Clock Buffer / Driver / Receiver / Translator
Embedded
No
Utilized Ic / Part
ADCLK854
Primary Attributes
2 Inputs, 12 Outputs
Secondary Attributes
CMOS, LVDS Outputs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
2 selectable differential inputs
Selectable LVDS/CMOS outputs
Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs
<12 mW per channel (100 MHz operation)
54 fs rms integrated jitter (12 kHz to 20 MHz)
100 fs rms additive broadband jitter
2.0 ns propagation delay (LVDS)
135 ps output rise/fall (LVDS)
70 ps output-to-output skew (LVDS)
Sleep mode
Pin programmable control
1.8 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout
buffer optimized for low jitter and low power operation. Possible
configurations range from 12 LVDS to 24 CMOS outputs,
including combinations of LVDS and CMOS outputs. Three
control lines are used to determine whether fixed blocks of
outputs (three banks of four) are LVDS or CMOS outputs.
The ADCLK854 offers two selectable inputs and a sleep mode
feature. The IN_SEL pin state determines which input is fanned
out to all the outputs. The SLEEP pin enables a sleep mode to
power down the device.
The inputs accept various types of single-ended and differential
logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.
Table 8 provides interface options for each type of connection.
This device is available in a 48-pin LFCSP package. It is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
1.8 V, 12-LVDS/24-CMOS Output,
Low Power Clock Fanout Buffer
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
CTRL_A
CTRL_B
CTRL_C
IN_SEL
SLEEP
CLK0
CLK0
CLK1
CLK1
V
REF
ADCLK854
FUNCTIONAL BLOCK DIAGRAM
V
S
/2
©2009 Analog Devices, Inc. All rights reserved.
LVDS/
CMOS
LVDS/
CMOS
LVDS/
CMOS
Figure 1.
ADCLK854
OUT0 (OUT0A)
OUT0 (OUT0B)
OUT1 (OUT1A)
OUT1 (OUT1B)
OUT2 (OUT2A)
OUT2 (OUT2B)
OUT3 (OUT3A)
OUT3 (OUT3B)
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT9 (OUT9A)
OUT9 (OUT9B)
OUT10 (OUT10A)
OUT10 (OUT10B)
OUT11 (OUT11A)
OUT11 (OUT11B)
www.analog.com

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ADCLK854/PCBZ Summary of contents

Page 1

FEATURES 2 selectable differential inputs Selectable LVDS/CMOS outputs LVDS (1.2 GHz CMOS (250 MHz) outputs <12 mW per channel (100 MHz operation rms integrated jitter (12 kHz to 20 MHz) 100 fs rms ...

Page 2

ADCLK854 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Characteristics ............................................................. 3 Timing Characteristics ................................................................ 4 Clock Characteristics ................................................................... 5 Logic and ...

Page 3

SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical (Typ) values are given for V = 1.8 V and T S the full V = 1.8 V ± 5% and T = −40°C to +85°C variation, unless otherwise noted. Input slew rate > 1 V/ns, ...

Page 4

ADCLK854 TIMING CHARACTERISTICS Table 2. Timing Characteristics Parameter LVDS OUTPUTS Output Rise/Fall Time Propagation Delay, Clock-to-LVDS Output Temperature Coefficient 1 Output Skew LVDS Outputs in the Same Bank All LVDS Outputs On the Same Part Across Multiple Parts Additive Time ...

Page 5

CLOCK CHARACTERISTICS Table 3. Clock Output Phase Noise Parameter CLOCK-TO-LVDS ABSOLUTE PHASE NOISE 1000 MHz CLOCK-TO-CMOS ABSOLUTE PHASE NOISE 200 MHz LOGIC AND POWER CHARACTERISTICS Table 4. Control Pin Characteristics Parameter Symbol 1 CONTROL PINS (IN_SEL, CTRL_x, SLEEP) Logic 1 ...

Page 6

ADCLK854 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage V to GND S Inputs CLKx and CLKx CMOS Inputs Outputs Maximum Voltage Voltage Reference Voltage (V ) REF Operating Temperature Ambient Range Junction Storage Temperature Range Stresses above those listed ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUT11 (OUT11B) OUT11 (OUT11A) Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 V Reference Voltage. REF 2 CLK0 Input (Negative CLK0 Input (Positive 18, 24, 30, V Supply Voltage. ...

Page 8

ADCLK854 Pin No. Mnemonic Description 26 OUT7 (OUT7A) True Side of Differential LVDS Output 7, or CMOS Output 7 on Channel A. 27 OUT6 (OUT6B) Complementary Side of Differential LVDS Output 6, or CMOS Output 6 on Channel B. 28 ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS 25°C, unless otherwise noted CH2 100mV M 200ps 10.0GS/s Figure 3. LVDS Output Waveform @ 1200 MHz 2.3 2.2 2.1 2.0 1.9 1.8 1.7 0.1 0.3 0.5 0.7 ...

Page 10

ADCLK854 900 800 700 600 500 400 INPUT FREQUENCY (MHz) Figure 9. LVDS Differential Output Swing vs. Input Frequency 350 325 300 275 250 225 200 175 150 125 100 200 400 600 800 1000 ...

Page 11

CH1 300mV 1.25ns/DIV Figure 15. CMOS Output Waveform @ 200 MHz (10 pF Load) 1.9 1.8 25°C 1.7 1.6 85°C 1.5 1.4 1.3 1.2 1.1 50 100 150 FREQUENCY (MHz) Figure 16. CMOS Output Swing vs. Frequency by Temperature ...

Page 12

ADCLK854 FUNCTIONAL DESCRIPTION The ADCLK854 accepts a clock input from one of two inputs and distributes the selected clock to all output channels. The outputs are grouped into three banks of four and can be set to either LVDS or ...

Page 13

... The layout of the ADCLK854 evaluation board (ADCLK854/PCBZ) provides a good layout example. Exposed Metal Paddle The exposed metal paddle on the ADCLK854 package is an electrical connection as well as a thermal enhancement ...

Page 14

ADCLK854 APPLICATIONS INFORMATION USING THE ADCLK854 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling ...

Page 15

This can be useful when driving long trace lengths on less critical networks 50Ω 10Ω CMOS Figure 27. CMOS Output with Far End Termination Because of the limitations of single-ended ...

Page 16

... ORDERING GUIDE Model Temperature Range 1 ADCLK854BCPZ −40°C to +85°C 1 ADCLK854BCPZ-REEL7 −40°C to +85°C ADCLK854/PCBZ RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 MAX 7.00 BSC SQ 0.60 MAX ...

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