AD9516-5/PCBZ Analog Devices Inc, AD9516-5/PCBZ Datasheet - Page 6

• Manufacturer Part Number: AD9516-5/PCBZ
• Description: Clock IC With 2.5GHz On-chip VCO EB
• Manufacturer: Analog Devices Inc

Specifications of AD9516-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-5
• Primary Attributes: 2 Inputs, 14 Outputs
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
1
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
LVDS CLOCK OUTPUTS
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V
OUT6, OUT7, OUT8, OUT9
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Input Frequency
Input Sensitivity, Differential
Input Common-Mode Range, V
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Input Level, Differential
Input Common-Mode Voltage, V
Output Frequency, Maximum
Output High Voltage (V
Output Low Voltage (V
Output Differential Voltage (V
Output Frequency, Maximum
Differential Output Voltage (V
Delta V
Output Offset Voltage (V
Delta V
Short-Circuit Current (I
OD
OS
SA
OL
OH
, I
)
OS
)
SB
)
)
OD
OD
CMR
CM
)
)
Min
0
0
1.3
1.3
3.9
550
247
1.125
Min
2400
VS_LVPECL −
1.12
VS_LVPECL −
2.03
800
1
1
Typ
150
1.57
150
4.7
2
Max
2.4
1.6
2
1.8
1.8
5.7
Typ
VS_LVPECL −
0.98
VS_LVPECL −
1.77
790
360
1.24
14
Rev. 0 | Page 6 of 76
Unit
GHz
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
CM
.
Max
VS_LVPECL −
0.84
VS_LVPECL −
1.49
980
454
25
1.375
25
24
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider enabled)
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider
Measured at 2.4 GHz; jitter performance is improved with
slew rates > 1 V/ns
Larger voltage swings can turn on the protection diodes
and can degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Unit
MHz
V
V
mV
MHz
mV
mV
V
mV
mA
Test Conditions/Comments
Termination = 50 Ω to VS_LVPECL − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 20 for
amplitude vs. frequency; the maximum
output frequency is limited by the
maximum frequency at the CLK inputs
Measured at dc; see Figure 20 for
amplitude vs. frequency
Measured at dc; see Figure 20 for
amplitude vs. frequency
Measured at dc; see Figure 20 for
amplitude vs. frequency
Differential termination 100 Ω @ 3.5 mA
Differential (OUT, OUT)
See Figure 21; the LVDS outputs can
toggle at higher frequencies, but the
output amplitude may not meet
the V
V
differential pair at the default
amplitude setting with output driver
not toggling; see Figure 21 for variation
over frequency
The absolute value of the difference
between V
is high vs. when the complementary
output is high
(V
at the default amplitude setting with
output driver not toggling
The absolute value of the difference
between V
is high vs. when the complementary
output is high
Output shorted to GND
OH
OH
− V
+ V
OD
OL
specification
OL
measurement across a
)/2 across a differential pair
OD
OS
when the normal output
when the normal output