AD9516-5/PCBZ Analog Devices Inc, AD9516-5/PCBZ Datasheet - Page 30

• Manufacturer Part Number: AD9516-5/PCBZ
• Description: Clock IC With 2.5GHz On-chip VCO EB
• Manufacturer: Analog Devices Inc

Specifications of AD9516-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-5
• Primary Attributes: 2 Inputs, 14 Outputs
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
There are several configurable modes of reference switchover.
The switchover can be performed manually or automatically.
Manual switchover is performed either through Register 0x01C
or by using the REF_SEL pin. The automatic switchover occurs
when REF1 disappears. The switchover deglitch feature ensures
that the PLL does not receive rising edges that are far out of
alignment with the newly selected reference.
There are two automatic reference switchover modes (0x01C):
• Prefer REF1. Switch from REF1 to REF2 when REF1
• Stay on REF2. Automatically switch to REF2 if REF1 disappears
In automatic mode, REF1 is monitored by REF2. If REF1
disappears (two consecutive falling edges of REF2 without an
edge transition on REF1), REF1 is considered missing. On the
next subsequent rising edge of REF2, REF2 is used as the
reference clock to the PLL. If 0x01C[3] = 0b (default), when
REF1 returns (four rising edges of REF1 without two falling
edges of REF2 between the REF1 edges), the PLL reference
switches back to REF1. If 0x01C[3] = 1b, the user can control
when to switch back to REF1. This is done by programming the
part to manual reference select mode (0x01C[4] = 0b) and by
ensuring that the registers and/or the REF_SEL pin are set to
select the desired reference. Automatic mode can be reenabled
when REF1 is reselected.
Manual switchover requires a valid clock on the reference input
being switched to or that the deglitching feature be disabled
(0x01C[7]).
Reference Divider R
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16,383 by
writing to 0x011 and 0x012. (Both R = 0 and R = 1 give divide-by-1.)
The output of the R divider goes to one of the PFD inputs to be
compared with the VCO frequency divided by the N divider.
The frequency applied to the PFD must not exceed the maximum
allowable frequency. The antibacklash pulse setting should also
be set according to Table 2 for a given PFD frequency.
The R divider has its own reset. R divider can be reset using the
shared reset bit of the R, A, and B counters. It can also be reset
by a SYNC operation.
VCXO/VCO Feedback Divider N: P, A, B
The N divider is a combination of a prescaler (P) and two
counters, A and B. The total divider value is
where P can be 2, 4, 8, 16, or 32.
Prescaler
The prescaler of the AD9516 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)
disappears. Return to REF1 from REF2 when REF1 returns.
but do not switch back to REF1 if it reappears. The reference
can be set back to REF1 manually at an appropriate time.
N = (P × B) + A
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mode where the prescaler divides by P and (P + 1) {2 and 3, 4
and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 49, 0x016[2:0]. Not all modes are
available at all frequencies (see Table 2).
When operating the AD9516 in dual modulus mode, P/(P + 1),
the equation used to relate the input reference frequency to the
VCO output frequency is
However, when operating the prescaler in FD Mode 1,
FD Mode 2, or FD Mode 3, the A counter is not used (A = 0)
and the equation simplifies to
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.
By using combinations of DM and FD modes, the AD9516 can
achieve values of N all the way down to N = 1. Table 24 shows
how a 10 MHz reference input may be locked to any integer
multiple of N.
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode P = 2 with B = 6, use the dual modulus mode 2/3
with A = 0, B = 6, or use the dual modulus mode 4/5 with
A = 0, B = 3.
A and B Counters
The B counter must be ≥3 or bypassed, and unlike the R counter,
A = 0 is actually zero.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) specified
in Table 2. This is the prescaler input frequency (external VCO
or CLK) divided by P. For example, dual-modulus P = 8/9 mode is
not allowed if the external VCO frequency is >2400 MHz because
the frequency going to the A counter and B counter is too high.
When the B counter is bypassed (B = 1), the A counter should
be set to zero, and the overall resulting divide is equal to the
prescaler setting, P. The possible divide ratios in this mode are
1, 2, 3, 4, 8, 16, and 32.
Although manual reset is not normally required, the A/B counters
have their own reset bit. Alternatively, the A and B counters can be
reset using the shared reset bit of the R, A, and B counters. Note
that these reset bits are not self-clearing.
R, A, and B Counters: SYNC Pin Reset
The R, A, and B counters can also be reset simultaneously
through the SYNC pin. This function is controlled by 0x019[7:6]
(see
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See 0x019 in Table 49.
Table 49
f
f
VCO
VCO
= (f
= (f
REF
REF
). The
/R) × (P × B + A) = f
/R) × (P × B) = f
SYNC pin reset is disabled by default.
REF
× N/R
REF
× N/R