AD9516-5/PCBZ Analog Devices Inc, AD9516-5/PCBZ Datasheet - Page 5

• Manufacturer Part Number: AD9516-5/PCBZ
• Description: Clock IC With 2.5GHz On-chip VCO EB
• Manufacturer: Analog Devices Inc

Specifications of AD9516-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-5
• Primary Attributes: 2 Inputs, 14 Outputs
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
PRESCALER (PART OF N DIVIDER)
PLL DIVIDER DELAYS
NOISE CHARACTERISTICS
PLL DIGITAL LOCK DETECT WINDOW
1
2
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Prescaler Input Frequency
Prescaler Output Frequency
000
001
010
011
100
101
110
111
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Means Within the LBW
of the PLL)
PLL Figure of Merit (FOM)
Required to Lock (Coincidence of Edges)
To Unlock After Lock (Hysteresis)
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
2
2
Min
Typ
Off
330
440
550
660
770
880
990
−165
−162
−151
−143
−220
3.5
7.5
3.5
7
15
11
Rev. 0 | Page 5 of 76
Max
300
600
900
600
1000
2400
3000
3000
300
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
A, B counter input frequency (prescaler input frequency
divided by P)
Register 0x019: R[5:3], N[2:0]; see Table 49
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the
value of the N divider)
Reference slew rate > 0.25 V/ns; FOM +10 log(f
an approximation of the PFD/CP in-band phase noise
(in the flat region) inside the PLL loop bandwidth; when
running closed loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N)
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by 0x017[1:0] and 0x018[4]
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
AD9516-5
PFD
) is