AD9516-5/PCBZ Analog Devices Inc, AD9516-5/PCBZ Datasheet - Page 36

• Manufacturer Part Number: AD9516-5/PCBZ
• Description: Clock IC With 2.5GHz On-chip VCO EB
• Manufacturer: Analog Devices Inc

Specifications of AD9516-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-5
• Primary Attributes: 2 Inputs, 14 Outputs
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
Table 26. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
0x1E1[0] = 0b
0x192[1] = 1b
0x195[1] = 1b
0x198[1] = 1b
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, and 6) and
the division of the channel divider. Table 27 and Table 28 indicate
how the frequency division for a channel is set. For the LVPECL
outputs, there is only one divider per channel. For the LVDS/
CMOS outputs, there are two dividers (X.1, X.2) cascaded
per channel.
Table 27. Frequency Division for Divider 0 to Divider 2
VCO Divider
Setting
2 to 6
2 to 6
2 to 6
VCO Divider
VCO Divider
Table 28. Frequency Division for Divider 3 and Divider 4
VCO Divider
Setting
2 to 6
2 to 6
2 to 6
Bypass
Bypass
Bypass
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 1 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 47 through Table 57).
Bypassed
Bypassed
Channel Divider Setting
X.1
Bypass
2 to 32
2 to 32
1
2 to 32
2 to 32
Channel
Divider
Setting
Don’t care
Bypass
2 to 32
Bypass
2 to 32
Selection
VCO divider selected
Direct to output OUT0, OUT1
Direct to output OUT2, OUT3
Direct to output OUT4, OUT5
X.2
Bypass
Bypass
2 to 32
1
1
2 to 32
CLK Direct
to Output
Setting
Enable
Disable
Disable
No
No
Resulting Frequency
Division
(2 to 6) × (1) × (1)
(2 to 6) × (2 to 32) × (1)
(2 to 6) × (2 to 32) ×
(2 to 32)
1
(2 to 32) × (1)
2 to 32 × (2 to 32)
Frequency Division
1
(2 to 6) × (1)
(2 to 6) × (2 to 32)
1
2 to 32
Rev. 0 | Page 36 of 76
VCO Divider
The VCO divider provides frequency division between the
external CLK input and the clock distribution channel dividers.
The VCO divider can be set to divide by 2, 3, 4, 5, or 6 (see
Table 55, 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving six
LVPECL outputs (OUT0 to OUT5). Table 29 gives the register
locations used for setting the division and other functions of
these dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting
of the DCCOFF bits.
Table 29. Setting D
Divider
0
1
2
Note that the value stored in the register equals the number of
cycles minus one. For example, 0x190[7:4] = 0001b equals two
low cycles (M = 2) for Divider 0.
Channel Frequency Division (0, 1, and 2)
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, D
(four bits each, representing decimal 0 to 15), where
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, D
Otherwise, D
each channel divider to divide by any integer from 1 to 32.
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
•
•
•
•
The DCC function is enabled by default for each channel
divider. However, the DCC function can be disabled individually
for each channel divider by setting the DCCOFF bit for that
channel.
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
What the M and N values for the channel are.
If the DCC is enabled.
If the VCO divider is used.
The CLK input duty cycle.
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
X
= (N + 1) + (M + 1) = N + M + 2. This allows
X
for Divider 0, Divider 1, and Divider 2
X
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
, is set by the values of M and N
X
= 1.
Bypass
0x191[7]
0x194[7]
0x197[7]
DCCOFF
0x192[0]
0x195[0]
0x198[0]