AD9516-5/PCBZ Analog Devices Inc, AD9516-5/PCBZ Datasheet - Page 16

• Manufacturer Part Number: AD9516-5/PCBZ
• Description: Clock IC With 2.5GHz On-chip VCO EB
• Manufacturer: Analog Devices Inc

Specifications of AD9516-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-5
• Primary Attributes: 2 Inputs, 14 Outputs
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 17. Pin Function Descriptions
Pin No.
1, 11, 12,
30, 31, 32,
38, 49, 50,
51, 57,
60, 61
2
3
4
5
6
7
8
9, 10, 15,
18, 19, 20
13
14
Input/
Output
I
O
O
I
O
O
I
I
I
I
Pin Type
Power
3.3 V CMOS
3.3 V CMOS
Power
Loop filter
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Differential
clock input
Differential
clock input
REF_SEL
NOTES
1. NC = NO CONNECT.
2. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
REFMON
STATUS
SYNC
Mnemonic
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
NC
CLK
CLK
SCLK
VCP
CLK
CLK
CP
NC
NC
NC
VS
LD
VS
VS
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Description
3.3 V Power Pins.
Reference Monitor (Output). This pin has multiple selectable outputs;
see Table 49 0x01B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 49 0x01A.
Power Supply for Charge Pump (CP); VS < VCP < 5.25 V.
Charge Pump (Output). This pin connects to an external loop filter. This pin can be
left unconnected if the PLL is not used.
Status (Output). This pin has multiple selectable outputs; see Table 49, 0x017.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
No Connection. These pins can be left floating.
Along with CLK, this is the differential input for the clock distribution section.
Along with CLK, this is the differential input for the clock distribution section.
If a single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor
from CLK to ground.
Figure 6. Pin Configuration
Rev. 0 | Page 16 of 76
(Not to Scale)
AD9516-5
TOP VIEW
LVPECL LVPECL
LVPECL LVPECL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
GND
OUT2
OUT2
VS_LVPECL
OUT3
OUT3
VS
GND
OUT9 (OUT9B)
OUT9 (OUT9A)
OUT8 (OUT8B)
OUT8 (OUT8A)