FPBL10SH60 Fairchild Semiconductor, FPBL10SH60 Datasheet
FPBL10SH60
Specifications of FPBL10SH60
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FPBL10SH60 Summary of contents
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... In addition the incorporated HVIC facilitates the use of single-supply drive topology enabling the FPBL10SH60 to be driven by only one drive supply voltage without negative bias. External View and Marking Information Top View ...
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... Resistor for Short-circuit Current Detection Connection Connection Connection 13 W Output Terminal for W Phase 14 V Output Terminal for V Phase 15 U Output Terminal for U Phase 16 N Negative DC–Link Input ©2002 Fairchild Semiconductor Corporation Top View Fig. 2. Pin Description V S(U) V B(U) V CC(UH) IN (UH) V S(V) V B(V) V CC(VH) ...
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... Inverter power side ( (13) - (17) pins) is composed of two inverter dc-link input terminals and three inverter output terminals. 3. Inverter high-side ( (18) - (30) pins) is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT. ©2002 Fairchild Semiconductor Corporation Pin Description W ...
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... Fault Output Current Current Sensing Input Voltage V Total System Item Self Protection Supply Voltage Limit (Short Circuit Protection Capability) Module Case Operation Temperature Storage Temperature Isolation Voltage ©2002 Fairchild Semiconductor Corporation Symbol Condition V Applied Link DC V Applied between P- N PN(Surge) V CES ± ...
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... V CC(L) COM (L) IN (UL) IN (VL) IN (WL FOD ©2002 Fairchild Semiconductor Corporation Case Temperature (T ) Detecting Point Fig Measurement Point c V S(U) V B(U) V CC(UH) IN (UH) V S(V) V B(V) V CC(VH) IN (VH) COM (H) Ceramic Substate V S(W) V B(W) V CC(WH) IN (WH) Rev. B1, February 2002 ...
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... IC OFF internally. For the detailed information, please see Fig. 5. ©2002 Fairchild Semiconductor Corporation Condition Each IGBT under Inverter Operating Condition (Note 2) Each FWDi under Inverter Operating Condition (Note 2) Ceramic Substrate (per 1 Module) Thermal Grease Applied ), please refer to Fig ...
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... I 90% I IN(ON) IN(ON) 10 (a) Turn-on (a) Turn- 100V/div. : 100V/div time : 100ns/div. time : 100ns/div. (a) Turn-on (a) Turn-on Fig. 6. Experimental Results of Switching Waveforms Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), T ©2002 Fairchild Semiconductor Corporation C(ON) C(ON 10 IN(OFF) IN(OFF) Fig 5. Switching Time Definition 5A/div ...
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... SC trip-level of about 15A. Please refer to Fig. 7 which shows the current sensing characteristics according to sensing resistor R 5. The fault-out pulse width t depends on the capacitance value of C FOD ©2002 Fairchild Semiconductor Corporation Condition Applied between COM CC(H) ...
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... Fig. 7. Relationship between Sensing Resistor and SC Trip Current for Short-Circuit Protection ( ©2002 Fairchild Semiconductor Corporation Sensing Resistor Rating Current(10A Rev. B1, February 2002 ...
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... Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction. 7. Avoid one side tightening stress. Fig.9 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to be damaged. Fig. 9. Mounting Screws Torque Order (1 ©2002 Fairchild Semiconductor Corporation Condition Recommended 10kg•cm Recommended 0.98N•m (Note Fig ...
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... The logic input is compatible with standard CMOS or LSTTL outputs coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each P P SPM gating input pin would be recommended that the bootstrap diode, D ©2002 Fairchild Semiconductor Corporation Condition V Applied between Applied between V - COM CC ...
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... Gate-Emitter Voltage Control Supply Voltage Output Current Fault Output Signal P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt fault signal P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current Fig. 12. Under-Voltage Protection (High-side) ©2002 Fairchild Semiconductor Corporation detect ...
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... Fig. 14. Recommended CPU I/O Interface Circuit ©2002 Fairchild Semiconductor Corporation Detection Reference Voltage (0.5V) RC Filter Delay P3 5V-Line 4.7k 4.7k 4.7k 1nF 0.47nF 1.2nF should be placed on the SPM pins and on the both sides of CPU and SPM (XX) P8 FPBL10SH60 , , (UH) (VH) (WH (UL) (VL) (WL Rev. B1, February 2002 ...
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... Fig. 15. Recommended Bootstrap Operation Circuit and Parameters ©2002 Fairchild Semiconductor Corporation One-leg Diagram of FPBL10SH60 One-leg Diagram of FPBL10SH60 Vcc Vcc VB VB 0.1uF 0.1uF COM COM VS VS Vcc Vcc IN IN OUT OUT COM COM P P Inverter ...
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... P&N pins is recommended. 11. Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays recommended that the distance be 5cm at least ©2002 Fairchild Semiconductor Corporation Gating UL Gating VL ...
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... Detailed Package Outline Drawings ©2002 Fairchild Semiconductor Corporation Rev. B1, February 2002 ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FAST Bottomless™ FASTr™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DenseTrench™ GTO™ ...