FPAL20SM60 Fairchild Semiconductor, FPAL20SM60 Datasheet - Page 15

• Manufacturer Part Number: FPAL20SM60
• Description: IGBT Transistors 600V/20A/SPM
• Manufacturer: Fairchild Semiconductor

Specifications of FPAL20SM60

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2002 Fairchild Semiconductor Corporation
Note
1. R
2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is
3. V
4. C
5. V
6. Each input signal line should be pulled up to the 5V power supply with approximately 4.7k
7. To prevent errors of the protection function, the wiring around R
8. In the short-circuit protection circuit, please select the R
9. Each capacitor should be mounted as close to the pins of the SPM as possible.
10.To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency non-
11.Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and
Tem p. Monitoring
pin.
possible.
refer to Fig. 15.
then t
depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a 0.22~2nF by-pass capacitor
should be used across each power supply connection terminals.
Example: R
inductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended.
the relays. It is recommended that the distance be 5cm at least
FO
FO
R
P
SP15
S
C
R
S
PL
output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7k
output pulse width should be determined by connecting an external capacitor(C
R
FO
S
/R
of around 7 times larger than bootstrap capacitor C
R
S
= 300 s (typ.)) Please refer to the note 5 for calculation method.
P
C
SC
PH
C
R
coupling at each SPM input is recommended in order to prevent input signals’ oscillation and it should be as close as possible to each SPM input
= 56 , R
PF
P
5V line
C
R
PL
P
C
SP05
C
R
PL
P
5V line
C
R
F
PL
P
= 3.9k and C
C
SPC05
R
R
C
C
SC
C
TH
R
BPF
FOD
SC
F
SC
(1) V
(2) COM
(3) IN
(4) IN
(5) IN
(6) V
(8) C
(7) C
(9) R
(10) NC
(11) V
(12) R
= 1nF)
FO
CC(L)
FOD
SC
SC
(UL)
(VL)
(WL)
TH
TH
(L)
Gating WL
Gating UL
Gating VL
THERMISTOR
Fault
V
COM
IN
IN
IN
V
C
C
CC
(FO)
F
(FOD)
(SC)
(WL)
(UL)
(VL)
C
Fig. 17. Application Circuit
(L)
BS
SC
Wout
Uout
Vout
is recommended.
time constant in the range 3~4 s. R
SC
, R
(13)
F
W
and C
CPU
M
(14)
SC
V
should be as short as possible.
(15)
FOD
U
) between C
resistance (other RC coupling circuits at each input may be needed
-
(16)
Gating UH
Gating WH
Gating VH
N
F
C
Vdc
DCS
should be at least 30 times larger than R
HO
HO
HO
VB
VS
VB
VS
VB
VS
FOD
COM
COM
COM
Vcc
Vcc
Vcc
+
(17) P
(pin7) and COM
IN
IN
IN
COM
V
V
V
CC(WH)
CC(UH)
IN
IN
CC(VH)
IN
V
V
V
V
V
V
B(W)
(WH)
B(U)
(UH)
S(U)
S(W)
B(V)
(VH)
S(V)
(H)
(29)
(28)
(27)
(30)
(25)
(26)
(20)
(19)
(18)
(24)
(23)
(22)
(21)
C
C
C
(L)
BSC
BSC
BSC
D
D
D
(pin2). (Example : if C
BS
BS
BS
C
C
C
BS
BS
BS
C
SPC15
R
R
R
BS
BS
BS
15V line
C
SP15
SC
resistance. Please
. (Recommended
C
R
5V line
PH
Rev. B, February 2002
P
FOD
C
R
PH
P
C
R
PH
= 5.6 nF,
P
R
S
R
S
R
S