FSAC20SH60 Fairchild Semiconductor, FSAC20SH60 Datasheet
FSAC20SH60
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FSAC20SH60 Summary of contents
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... In addition the incorporated HVIC facilitates the use of single-supply drive topology enabling the FSAC20SH60 to be driven by only one drive supply voltage without opto-couplers. Inverter current sensing application can be achieved due to devided negative dc terminals. ...
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... IN (WH) (13) IN (VH) (14) IN (UH) (15) IN (DB) (16) V B(W) (17) V S(W) (18) V B(V) (19) V S(V) (20) V B(U) (21) V S(U) (22) R (23) S (24) NC ©2003 Fairchild Semiconductor Corporation Bottom View Fig. 2. Pin Configuration (25 (26 (27 (28 (29 (30) W (31) V (32) U (33) P (34 (35) B Rev. B, May 2003 ...
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... Negative DC-Link Input for V phase Negative DC-Link Input for U phase Output for W Phase 31 V Output for V Phase 32 U Output for U Phase 33 P Positive DC-Link Input 34 P Positive DC-Link Output Collector of Brake IGBT ©2003 Fairchild Semiconductor Corporation Pin Description Rev. B, May 2003 ...
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... Inverter low-side is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving and protection functions. 2) Inverter high-side is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT. Fig. 3. Internal Equivalent Circuit and Input/Output Pins ©2003 Fairchild Semiconductor Corporation ( ...
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... Fault Output Current Current Sensing Input Voltage V Total System Item Self Protection Supply Voltage Limit (Short Circuit Protection Capability) Module Case Operation Temperature Storage Temperature Isolation Voltage ©2003 Fairchild Semiconductor Corporation (T = 25°C, Unless Otherwise Specified) J Symbol Condition V Applied between P Applied between N ...
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... IC OFF internally. For the detailed information, please see Fig. 4. ©2003 Fairchild Semiconductor Corporation Condition Each IGBT under Inverter Operating Condition Each FWDi under Inverter Operating Condition Brake IGBT Brake Diode Converter Diode (T = 25° ...
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... 90% I 90% I IN(ON) IN(ON) 10 (a) Turn-on (a) Turn- 100V/div time : 0.1us/div. (a) turn-on Fig. 5. Experimental Results of Switching Waveforms Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), T ©2003 Fairchild Semiconductor Corporation C(ON) C(ON 10 IN(OFF) IN(OFF) Fig. 4. Switching Time Definition : 10A/div OFF OFF t ...
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... SC trip-level of about 30A at the shunt resistors (R relationship between the external sensing resistor (R 4. The fault-out pulse width t depends on the capacitance value of C FOD the temperature of thermistor. TH ©2003 Fairchild Semiconductor Corporation Condition Applied between V - COM CC Applied between ...
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... Fig Variation by Change of Shunt Resistors (R SC ① ① ① ① @ around 100% Rated Current Trip (I ② ② ② ② @ around 150% Rated Current Trip (I ©2003 Fairchild Semiconductor Corporation R-T Curve Temperature T [ ℃ ① ① ① ① ② ② ② ② ...
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... Supply Voltage Control Supply Voltage V High-side Bias Voltage Blanking Time for Preventing t Arm-short PWM Input Signal f Input ON Threshold Voltage V IN(ON) Input OFF Threshold Voltage V IN(OFF) ©2003 Fairchild Semiconductor Corporation Condition Recommendation 17.9 Kg•cm Recommendation 1.75 N•m (1) (1) Condition V Applied between Applied between V ...
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... Gate-Emitter Voltage Control Supply Voltage Output Current Fault Output Signal P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt fault signal P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current Fig. 10. Under-Voltage Protection (High-side) ©2003 Fairchild Semiconductor Corporation detect ...
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... P3 : IGBT gate interrupt / Fault signal generation P4 : IGBT is slowly turned off P5 : IGBT OFF signal P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation P7 : IGBT OFF state P8 : Fault-output reset and normal operation start Fig. 11. Short-circuit Current Protection (Low-side Operation only) ©2003 Fairchild Semiconductor Corporation Detection ...
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... SPIM input is recommended in order to prevent input/output signals’ oscillation and it should be as close possible to each of SPIM pins. Fig. 12. Recommended CPU I/O Interface Circuit These Values depend Control Algorithm 15V-Line Ω 20 47uF 1000uF 0.1uF Fig. 13. Recommended Bootstrap Operation Circuit and Parameters ©2003 Fairchild Semiconductor Corporation 5V-Line 4.7k 2k 4.7k Ω Ω Ω Ω ...
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... P&N pins should be as short as possible. The use of a high frequency non- inductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended. 12) The stray inductance between N-pins ©2003 Fairchild Semiconductor Corporation A C Line (22) R (23) S (24) NC ...
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... Detailed Package Outline Drawings 3.0 Ø 4- 2.0 Ø ©2003 Fairchild Semiconductor Corporation 1.3 0.6 * 0.6t +0.10 75.7 - 0.30 67.2 ±0.15 65.5 ±0.15 35 +0.20 2- 4.3 Ø -0.00 Mounting-Hole 4.0 1 35.0 ±0.10 3.0 5.0 1.50 * 0.6t Name Plate -. Pin Coordinate Coordinate Pin # 0.0 ...
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... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet series™ ® Bottomless™ FAST CoolFET™ FASTr™ CROSSVOLT™ ...