LS-XP10-BASE-PC-N Lattice, LS-XP10-BASE-PC-N Datasheet - Page 8
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LS-XP10-BASE-PC-N
Manufacturer Part Number
LS-XP10-BASE-PC-N
Description
MCU, MPU & DSP Development Tools ispLEVER Base Lattic eXP-10 Std Dev Kit
Manufacturer
Lattice
Datasheet
1.M4A5-6432-10JNC.pdf
(62 pages)
Specifications of LS-XP10-BASE-PC-N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8
Output Macrocell
Output Macrocell
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”
Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)
Product
Product
Extra
Term
Extra
Term
Basic Product
Basic Product
Term Cluster
Term Cluster
0 Default
0 Default
n
Available Clusters
Available Clusters
Table 7. Logic Allocator for M4A(3,5)-32/32
n
C
C
C
C
C
C
C
C
C
C
C
C
0
1
2
3
4
5
6
0
1
2
3
4
C
C
C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
0
0
5
C
, C
, C
, C
1
2
3
4
5
6
7
1
2
3
4
5
6
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
1
1
6
, C
, C
, C
2
3
4
5
6
7
8
2
3
4
5
6
7
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
2
2
7
3
4
5
6
7
8
9
3
4
5
6
7
ispMACH 4A Family
a. Synchronous Mode
b. Asynchronous Mode
Output Macrocell
Output Macrocell
Prog. Polarity
n
Prog. Polarity
n
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
10
11
12
13
14
15
10
11
12
13
14
15
8
9
8
9
0 Default
0 Default
Logic Allocator
Logic Allocator
Available Clusters
Available Clusters
C
C
C
C
C
C
C
C
C
C
10
11
12
10
11
12
C
9
9
8
C
8
C
7
, C
, C
, C
, C
, C
, C
C
, C
, C
, C
, C
13
13
, C
C
8
C
10
10
, C
, C
, C
9
11
12
13
14
9
11
12
13
14
8
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
14
9
14
, C
10
10
9
11
11
, C
, C
12
13
14
15
12
13
14
15
, C
, C
, C
10
, C
, C
, C
, C
, C
, C
, C
, C
15
15
10
11
11
12
12
13
14
15
13
14
15
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