LS-XP10-BASE-PC-N Lattice, LS-XP10-BASE-PC-N Datasheet - Page 46

• Manufacturer Part Number: LS-XP10-BASE-PC-N
• Description: MCU, MPU & DSP Development Tools ispLEVER Base Lattic eXP-10 Std Dev Kit
• Manufacturer: Lattice

Specifications of LS-XP10-BASE-PC-N

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

100-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64)
Top View
PIN DESIGNATIONS
I/CLK = Input or Clock
GND = Ground
I
I/O
V
TDI
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
TRST = Test Reset
ENABLE = Program
46
CC
= Input/Output
= Input
= Supply Voltage
= Test Data In
B7
B6
B5
B4
B3
B2
B1
B0
C0
C1
C2
C3
C4
C5
C6
C7
IO/CLK0
I1/CLK1
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
GND
GND
GND
GND
GND
TMS
V CC
V CC
TCK
I/O8
I/O9
TDI
I5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ispMACH 4A Family
C
100-Pin PQFP
7
I/O Cell
PAL Block
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
GND
TD0
TRST
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
V CC
V CC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
ENABLE
GND
GND
G7
G6
G5
G4
G3
G2
G1
G0
F0
F1
F2
F3
F4
F5
F6
F7
17466G-031