LS-XP10-BASE-PC-N Lattice, LS-XP10-BASE-PC-N Datasheet - Page 45

• Manufacturer Part Number: LS-XP10-BASE-PC-N
• Description: MCU, MPU & DSP Development Tools ispLEVER Base Lattic eXP-10 Std Dev Kit
• Manufacturer: Lattice

Specifications of LS-XP10-BASE-PC-N

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

100-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48)
Top View
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
I/O
V
NC
TDI
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
CC
= Input/Output
= No Connect
= Input
= Supply Voltage
= Test Data In
C0
C1
A1
A0
B0
B1
B2
B3
B4
B5
B6
B7
I0/CLK0
I1/CLK1
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
GND
TMS
TCK
I/O6
I/O7
I/O8
I/O9
V
TDI
NC
NC
NC
NC
NC
NC
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
C
7
ispMACH 4A Family
100-Pin TQFP
I/O Cell
PAL Block
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
TDO
NC
NC
NC
I/O41
I/O40
I/O39
I/O38
I/O37
I/O36
I5/CLK3
GND
V
I4/CLK2
I/O35
I/O34
I/O33
I/O32
I/O31
I/O30
NC
NC
NC
NC
CC
F1
F0
E0
E1
E2
E3
E4
E5
E6
E7
D0
D1
17466G-029
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