C8051F206DK-G Silicon Laboratories Inc, C8051F206DK-G Datasheet - Page 129

• Manufacturer Part Number: C8051F206DK-G
• Description: MCU, MPU & DSP Development Tools MCU DEVELOPMENT KIT W/ GLOBAL POWER SPLY
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F206DK-G

• Processor To Be Evaluated: C8051F206
• Data Bus Width: 8 bit
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF1
R/W
Bit7
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 1 service routine if IT1 = 1. This flag is the inverse of the /INT1 input signal's logic level
when IT1 = 0.
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 signal will detect falling edge or active-low
level-sensitive interrupts.
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 input signal's logic level
when IT0 = 0.
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 signal will detect falling edge or active-low
level-sensitive interrupts.
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
TR1
R/W
Bit6
SFR Definition 17.1. TCON: Timer Control
TF0
R/W
Bit5
TR0
R/W
Bit4
Rev. 1.6
R/W
IE1
Bit3
R/W
IT1
Bit2
R/W
IE0
Bit1
C8051F2xx
R/W
IT0
Bit0
SFR Address:
Reset Value
00000000
0x88
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