PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 6

MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD

PAC-POWR607-EV

Manufacturer Part Number
PAC-POWR607-EV
Description
MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
Manufacturer
Lattice
Series
ispPAC®r
Datasheets

Specifications of PAC-POWR607-EV

Processor To Be Evaluated
ispPAC-POWR607
Interface Type
JTAG
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.96 V
Core Architecture
CPLD
Main Purpose
Power Management, Power Supply Supervisor/Tracker/Sequencer
Embedded
Yes, Other
Utilized Ic / Part
ispPAC-POWR607
Primary Attributes
-
Secondary Attributes
4.5 ~ 9 V Supply
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Figure 4-2. Internal Power-On Reset
V
V
V
TH
TL
T
Reset
State
Calibration
Start Up State
T
Analog
RST
T
START
4-6
T
T
BRO
POR
ispPAC-POWR607 Data Sheet
POR (Internal)
PLDCLK (Internal)
VMONs Ready (Internal)
VCC

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