PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 23

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 4-19. ispPAC-POWR607 ID Code
ispPAC-POWR607 Specific Instructions
There are 25 unique instructions specified by Lattice for the ispPAC-POWR607. These instructions are primarily
used to interface to the various user registers and the E
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 4-5.
PLD_ADDRESS_SHIFT – This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent
program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_DATA_SHIFT – This instruction is used to shift PLD data into the register prior to programming or reading.
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_INIT_ADDR_FOR_PROG_INCR – This instruction prepares the PLD address register for subsequent
PLD_PROG_INCR or PLD_VERIFY_INCR instructions.
PLD_PROG_INCR – This instruction programs the PLD data register for the current address and increments the
address register for the next set of data.
PLD_PROGRAM – This instruction programs the selected PLD AND/ARCH array column. The specific column is
preselected by using PLD_ADDRESS_SHIFT instruction. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PROGRAM_SECURITY – This instruction is used to program the electronic security fuse (ESF) bit. Programming
the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_VERIFY – This instruction is used to read the content of the selected PLD AND/ARCH array column. This
specific column is preselected by using PLD_ADDRESS_SHIFT instruction. This instruction also forces the outputs
into the OUTPUTS_HIGHZ.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR607 for a read cycle. This instruction also forces the outputs into the
OUTPUTS_HIGHZ.
BULK_ERASE – This instruction will bulk erase all E
POWR607. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction
also forces the outputs into the OUTPUTS_HIGHZ.
OUTPUTS_HIGHZ – This instruction turns off all of the open-drain output transistors. Pins that are programmed as
FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register
JTAG state.
PROGRAM_ENABLE – This instruction enables the programming mode of the ispPAC-POWR607. This instruction
also forces the outputs into the OUTPUTS_HIGHZ.
00147h = ispPAC-POWR607
MSB
0000 0000 0001 0100 0111 / 0000 0100 001 / 1
Part Number
(20 bits)
Lattice Semiconductor
JEDEC Manufacturer
Identity Code for
(11 bits)
4-23
2
CMOS bits (CFG, PLD, UES, and ESF) in the ispPAC-
2
CMOS non-volatile memory. Additional instructions are
LSB
per 1149.1-1990
Constant 1
(ispPAC-POWR607)
(1 bit)
ispPAC-POWR607 Data Sheet